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410 Commits

Author SHA1 Message Date
Jarred Allen
000f48cd75 Fix compile error in branch predictor 2021-04-29 14:36:56 -04:00
Shreya Sanghai
b554dc8e72 fixed bug in gshare, global and local history BP 2021-04-29 06:14:32 -04:00
Thomas Fleming
e091f430e0 Clean up PMA checker and begin PMP checker 2021-04-29 02:20:39 -04:00
Ross Thompson
14a69c1d06 Added the ability to exclude branch predictor. 2021-04-26 14:27:42 -05:00
Ross Thompson
a7e4d39ea1 Fixed issue with not saving the first cache block read on a miss spill. 2021-04-26 12:57:34 -05:00
Ross Thompson
44d28dbd1c Icache integrated! 
Merge branch 'icache-almost-working' into main
 2021-04-26 11:48:58 -05:00
bbracker
f921886451 merge cleanup; mem init is broken 2021-04-26 08:00:17 -04:00
bbracker
7947858481 it says I need to merge in order to pull 2021-04-26 07:46:24 -04:00
bbracker
8d77012995 progress on bus and lrsc 2021-04-26 07:43:16 -04:00
Ross Thompson
9e40fb072c Merge branch 'tests' into icache-almost-working 2021-04-25 21:25:36 -05:00
bbracker
46a1616079 thomas fixed it before I did 2021-04-24 09:38:52 -04:00
bbracker
5687ab1c96 do script refactor 2021-04-24 09:32:09 -04:00
Thomas Fleming
6f23858609 Fix HSIZE and HBURST signal widths in PMA checker 2021-04-23 20:11:43 -04:00
Ross Thompson
d7fea1ba3c almost working icache. 2021-04-23 16:47:23 -05:00
Ross Thompson
c9bdaceddb Fixed icache for 32 bit. 
Merge branch 'cache' into main
 2021-04-22 16:45:29 -05:00
Ross Thompson
04eb302925 Yes. The hack to not repeat the d memory operation fixed this issue. 2021-04-22 15:22:56 -05:00
Thomas Fleming
5bff582608 Write PCM to TVAL registers 2021-04-22 16:17:57 -04:00
Thomas Fleming
07770a46d8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-22 15:37:19 -04:00
Thomas Fleming
74fb1dccad Prepare to squash bad ahb accesses 2021-04-22 15:36:45 -04:00
Thomas Fleming
c055ab272d Clean up lint errors in fpu and muldiv 
booth.sv had an actual error where a signal was being assigned to too
many bits. muldiv has a lot of non blocking assignments, so I suppressed
those warnings so the linter output was readable.
 2021-04-22 15:36:03 -04:00
Domenico Ottolia
787ae978d7 Fix misa synthesis bug (for real now) 2021-04-22 15:35:20 -04:00
Thomas Fleming
e7822ce20c Implement first pass at the PMA checker 2021-04-22 15:34:02 -04:00
Thomas Fleming
805ac5dbd7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-22 13:20:12 -04:00
bbracker
c796547156 greatly improved PLIC register interface 2021-04-22 11:22:01 -04:00
Ross Thompson
7c8d2e9b78 Partially working icache. 
The current issue is a StallF is required to halt the icache from getting an updated PCF. However
if the dmemory is the reason for a stall it is possible for the icache stall to hold the d memory request continuously causing d memory to repeatedly read from memory.  This keeps StallF high and
the icache FSM is never allowed to complete.
 2021-04-22 10:20:36 -05:00
Thomas Fleming
d22f0f9d63 Refactor tlb_ram to use flop primitives 2021-04-22 01:52:43 -04:00
Thomas Fleming
4d4ca24640 Extend stall on leaf page lookups 2021-04-22 01:51:38 -04:00
Domenico Ottolia
939e36a151 Fix misa bug 2021-04-22 00:59:07 -04:00
Thomas Fleming
88bd151d55 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ifu/ifu.sv
 2021-04-21 20:01:08 -04:00
Thomas Fleming
70c801331a Implement virtual memory protection 2021-04-21 19:58:36 -04:00
Ross Thompson
50e893eec9 Fixed for the instruction spills. 2021-04-21 16:47:05 -05:00
Teo Ene
008b308b79 Fixed most relevant remaining synthesis compilation warnings with Ben 2021-04-21 16:06:27 -05:00
Ross Thompson
269ea7997c major progress. 
It's running the icache is imperas tests now.
Compressed does not work yet.
 2021-04-21 08:39:54 -05:00
Domenico Ottolia
d5f86fadac Add tests for sepc register 2021-04-20 23:50:53 -04:00
Ross Thompson
a861a37b72 Why was the linter messed up? 
There are a number of combo loops which need fixing outside the icache.  They may be fixed in main.
We get to instruction address 50 now!
 2021-04-20 22:06:12 -05:00
Ross Thompson
daa1ab9261 Progress on icache. Fixed some issues aligning the PC with instruction. Still broken. 2021-04-20 21:19:53 -05:00
Ross Thompson
649589ee2c Broken icache. Design is done. Time to debug. 2021-04-20 19:55:49 -05:00
Domenico Ottolia
e02ff60b07 Fix synthesis warnings for privileged unit (replace 'initial' settings) 2021-04-20 17:57:56 -04:00
Jarred Allen
59b340dac9 Merge branch 'main' into cache 2021-04-19 00:05:23 -04:00
Katherine Parry
204e5cb018 fixed synth bugs in fpu 2021-04-19 00:39:16 +00:00
Noah Boorstin
d0a137ce0c neat verilog thing 2021-04-18 17:48:51 -04:00
Jarred Allen
3868a82932 dcache lints 2021-04-15 21:13:56 -04:00
bbracker
11cf251378 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-15 21:09:27 -04:00
bbracker
195cead01c working GPIO interrupt demo 2021-04-15 21:09:15 -04:00
Domenico Ottolia
b1cd107a00 Add tests for scause and ucause 2021-04-15 19:41:25 -04:00
Domenico Ottolia
a149f2f3d8 Add support for vectored interrupts 2021-04-15 19:13:42 -04:00
Teo Ene
a9c6d357d8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-15 15:29:09 -05:00
Teo Ene
7a40c27b59 Quick fix to ahblite missing default statement done in class :) 2021-04-15 15:29:04 -05:00
Thomas Fleming
e8770e3eac Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/mmu/priority_encoder.sv
 2021-04-15 16:20:43 -04:00
Thomas Fleming
e838f0bb3d Change priority encoder to avoid extra assignment 2021-04-15 16:17:35 -04:00
Thomas Fleming
2c4682c4be Connect tlb and icache properly 2021-04-15 14:48:39 -04:00
Teo Ene
cefc8ea22b Temporary change to mmu/priority_encoder.sv 
Necessary to get synth working
Original HDL is still there, just commented out
 2021-04-15 13:37:12 -05:00
Katherine Parry
0bdd3efdd5 integraded the FMA into the FPU 2021-04-15 18:28:00 +00:00
Jarred Allen
7b4b1a31ef Merge branch 'main' into cache 2021-04-15 13:47:19 -04:00
Ross Thompson
534e3eaac8 Merge branch 'bpfixes' into main 2021-04-15 09:06:21 -05:00
Shreya Sanghai
75caa65df1 Cherry Pick merge of Shreya's localhistory predictor changes into main. 
fixed minor bugs in localHistory
 2021-04-15 09:04:36 -05:00
ShreyaSanghai
80fbd66113 added localHistoryPredictor 2021-04-15 08:58:22 -05:00
Shreya Sanghai
3696bf4f2c fixed bugs in global history to read latest GHRE 
Cherry pick Shreya's commits into main branch.
 2021-04-15 08:55:22 -05:00
bbracker
76f50d7a69 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-15 09:06:03 -04:00
bbracker
da22308e60 csri lint improvement 2021-04-15 09:05:53 -04:00
Jarred Allen
4d58f673b2 Add a comment to explain a detail 2021-04-14 23:14:59 -04:00
Thomas Fleming
d281ecd067 Remove imem from testbenches 2021-04-14 20:20:34 -04:00
Jarred Allen
c32fe09056 More icache bugfixes 2021-04-14 19:03:33 -04:00
Jarred Allen
757b64e487 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/cache/dmapped.sv
	wally-pipelined/src/cache/line.sv
	wally-pipelined/src/ifu/icache.sv
 2021-04-14 18:24:32 -04:00
bbracker
ccff1e6c99 rv64 interrupt servicing 2021-04-14 10:19:42 -04:00
Thomas Fleming
bb2d433971 Fix mmu lint errors 2021-04-13 19:19:58 -04:00
Thomas Fleming
a545dcb9ae Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-13 17:15:10 -04:00
Katherine Parry
e075dc2d13 Various bugs fixed in FMA 2021-04-13 18:27:13 +00:00
Thomas Fleming
ae888b5705 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ebu/pagetablewalker.sv
 2021-04-13 13:42:03 -04:00
Thomas Fleming
f0c926cf68 Move InstrPageFault to fetch stage 2021-04-13 13:39:22 -04:00
Thomas Fleming
08a84048b6 Add lru algorithm to TLB 2021-04-13 13:37:24 -04:00
Teo Ene
0bffac2c74 Various code syntax changes to bring HDL to a synthesizable level 2021-04-13 11:27:12 -05:00
Jarred Allen
95ad9a93a4 Merge branch 'main' into cache 2021-04-13 01:10:03 -04:00
Jarred Allen
357aed75ee A few more cache fixes 2021-04-13 01:07:40 -04:00
Ross Thompson
cb52820249 Fixed minor bug in muldiv which corrects the lint error. 2021-04-09 10:56:31 -05:00
Jarred Allen
6ce4d44ae1 Merge from branch 'main' 2021-04-08 17:19:34 -04:00
Katherine Parry
08f45eb076 fixed FPU lint warnings 2021-04-08 18:03:21 +00:00
Katherine Parry
ebf4915440 fixed FPU lint warnings 2021-04-08 17:55:25 +00:00
Domenico Ottolia
1bdfac6a77 Cause an Illegal Instruction Exception when attempting to write readonly CSRs 2021-04-08 05:12:54 -04:00
Thomas Fleming
bd310a55af Refactor TLB into multiple files 2021-04-08 03:24:10 -04:00
Thomas Fleming
b3795cef2e Provide attribution link for priority encoder 2021-04-08 03:05:06 -04:00
Thomas Fleming
e807f5d771 Implement support for superpages 2021-04-08 02:44:59 -04:00
Ross Thompson
7f12c7af90 Switch to use RV64IC for the benchmarks. 
Still not working correctly with the icache.

instr
addr   correct   got
 2021-04-07 19:12:43 -05:00
Ross Thompson
d901cfc848 Merge branch 'icache_bp_bug' into tests 
Not sure this merge is right.
 2021-04-06 21:46:40 -05:00
Ross Thompson
a5dc175ab2 Merge remote-tracking branch 'refs/remotes/origin/tests' into tests 2021-04-06 21:20:55 -05:00
Jarred Allen
4da2688c40 Fix another bug in icache 2021-04-06 17:47:00 -04:00
Jarred Allen
ecb2bc8163 Fix another bug in icache 2021-04-06 12:48:42 -04:00
bbracker
80a67dc906 declare memread signal 2021-04-05 08:13:01 -04:00
bbracker
eca92041e9 PLIC claim reg side effects now check for memread signal 2021-04-05 08:03:14 -04:00
bbracker
8f4da826fb plic subword access compliance 2021-04-04 23:10:33 -04:00
Katherine Parry
f41b5a2d38 Added missing files in FPU 2021-04-04 18:09:13 +00:00
bbracker
ce7b2314ef Yee hoo first draft of PLIC plus self-checking tests 2021-04-04 06:40:53 -04:00
Thomas Fleming
5946b860ca Comment out fpu from hart until module exists 2021-04-03 22:34:11 -04:00
Thomas Fleming
8f31e00f6a Merge branch 'mmu' into main 
Conflicts:
	wally-pipelined/src/wally/wallypipelinedhart.sv
 2021-04-03 22:12:52 -04:00
Thomas Fleming
ac89947e98 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-03 22:09:50 -04:00
Thomas Fleming
e04ad8f304 Fix extraneous page fault stall 2021-04-03 21:28:24 -04:00
Jarred Allen
4ebc991a65 Fix bug in icache 2021-04-03 18:10:54 -04:00
Katherine Parry
08b31f7b2a Integrated FPU 2021-04-03 20:52:26 +00:00
Ross Thompson
a743acd1fd Partial fix to the integer divide stall issue. 2021-04-02 15:32:15 -05:00
James E. Stine
e38e7aff8e Minor cleanup 2021-04-02 08:20:44 -05:00