James E. Stine
194c32defa
Update header for FPadd
2021-05-24 08:28:16 -05:00
Katherine Parry
55f22979ca
FSD and FLD imperas tests pass
2021-05-23 18:33:14 -04:00
Katherine Parry
71e4a10efb
FMV.D.X imperas test passes
2021-05-20 22:17:59 -04:00
bbracker
8554f2f3cd
plic implementation optimizations
2021-05-19 18:10:48 +00:00
Katherine Parry
409438bc95
floating point infinite loop removed from imperas tests
2021-05-18 10:42:51 -04:00
James E. Stine
49cc330bd9
Forgot initialization config for div - apologies
2021-05-17 17:12:27 -05:00
James E. Stine
96eca3287f
Add 32/64-bit shifter for update to shifter block
2021-05-17 17:02:13 -05:00
James E. Stine
97cbdae674
Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version
2021-05-17 16:48:51 -05:00
Thomas Fleming
fda439b51e
Fix comment
2021-05-14 08:06:07 -04:00
Thomas Fleming
1fc607b399
Remove busy-mmu and fix missing signal
2021-05-14 07:14:20 -04:00
Thomas Fleming
980c00fa64
Clean up MMU code
2021-05-14 07:12:32 -04:00
Thomas Fleming
1e0a5ef807
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-04 15:22:21 -04:00
bbracker
535046e494
small synthesis fixes
2021-05-04 15:21:01 -04:00
Thomas Fleming
37bba95500
Fix compiler warning in PMP checker
2021-05-04 15:18:08 -04:00
Ross Thompson
2aa4db470b
Fixed synthesis bug with icache valid bit.
2021-05-04 13:03:08 -05:00
Ross Thompson
87d3869a6e
Fixed icache pcmux control for handling miss spill miss.
2021-05-04 11:05:01 -05:00
Thomas Fleming
dac07e34cf
Fix bug in PMP checker
...
Now we only enforce PMP regions if at least one is non-null
2021-05-04 03:14:07 -04:00
Thomas Fleming
d7fa0903bc
Disable PMP checker to fix test loops
...
There is a bug in the PMP checker where S or U mode attempts to make a
memory access while no PMP registers are set. We currently treat this as
a failure, when this should instead be allowed.
2021-05-04 01:56:05 -04:00
Thomas Fleming
d53afc8510
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-03 23:15:39 -04:00
Domenico Ottolia
a7e89f43c1
Fix bug with IllegalInstrFaultM not getting correct value
2021-05-03 22:48:03 -04:00
Thomas Fleming
f78f2b3b5d
Adjust attributes in PMA checker
2021-05-03 21:58:32 -04:00
David Harris
96e90402c5
Rolled back fflush on uart. Use -syncio in Modelsim command line instead.
2021-05-03 20:04:44 -04:00
David Harris
062120f944
Flush uart print statements on \n
2021-05-03 19:51:51 -04:00
David Harris
743011194b
Flush uart print statements on \n
2021-05-03 19:41:37 -04:00
David Harris
8758b6efa1
Flush uart print statements on \n
2021-05-03 19:37:45 -04:00
David Harris
2f5649832a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 19:29:01 -04:00
David Harris
1f2da4c457
Flush uart print statements on \n
2021-05-03 19:25:28 -04:00
Ross Thompson
6a01ea9f2d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 16:57:36 -05:00
Ross Thompson
ed4f2ecb24
fixed subtle typo in icache fsm. Was messing up hit spill hit.
...
I believe the mibench qsort benchmark runs after this icache fix.
2021-05-03 16:55:36 -05:00
Domenico Ottolia
ab68933466
Fix bug that caused stvec to get the wrong value
2021-05-03 17:54:57 -04:00
Thomas Fleming
3f7061d557
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-03 17:38:13 -04:00
Thomas Fleming
86a93d77b4
Implement PMP checker and revise PMA checker
2021-05-03 17:37:42 -04:00
Thomas Fleming
00c3b5a033
Remove remnants of InstrReadC
2021-05-03 17:36:25 -04:00
Ross Thompson
0a44d4dd4e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 14:53:54 -05:00
Ross Thompson
e09ac73eaf
Removed combinational loops between icache and PMA checker.
2021-05-03 14:51:25 -05:00
Ross Thompson
7185905f7b
Reduced icache to 1 port memory.
2021-05-03 14:47:49 -05:00
Katherine Parry
3f05e31954
fpu warnings fixed/commented
2021-05-03 19:17:09 +00:00
Thomas Fleming
94d734cca9
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/src/ebu/ahblite.sv
2021-05-03 14:02:19 -04:00
Ross Thompson
12b978fec2
Eliminated extra register and fixed ports to icache.
...
Still need to support physical tag check and write in icache memory.
Still need to reduce to 1 port SRAM in icache.
I would like to refactor the icache code.
2021-05-03 12:04:54 -05:00
bbracker
8ec0d18444
merge conflict resolved -- Ross and I made the same fix
2021-05-03 10:10:42 -04:00
Ross Thompson
b57c187208
Fixed typo in ifu for bypassing branch predictor.
...
Fixed missing signal name in local history predictor.
2021-05-03 08:56:45 -05:00
David Harris
c9806fb472
Fixed lint error in div
2021-05-03 09:26:12 -04:00
bbracker
fb0910d9c0
ifu lint fixes
2021-05-03 09:25:22 -04:00
bbracker
acd99be7f8
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 09:23:52 -04:00
Katherine Parry
9252d08b41
fpu imperas tests run
2021-05-01 02:18:01 +00:00
bbracker
0d62440f60
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-30 06:26:35 -04:00
bbracker
9c08ce5359
rv32 plic test and lint fixes
2021-04-30 06:26:31 -04:00
Domenico Ottolia
830787e3e1
Make vectored interrupt trap handling work, and add tests for mtvec with vectored interrupts
2021-04-29 20:42:14 -04:00
Thomas Fleming
10c7260980
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-29 16:30:00 -04:00
ushakya22
de23edcfb9
fix to pcm bug
2021-04-29 15:21:08 -04:00
