Rose Thompson
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c0e02ae190
|
Found another bug in the RTL's Zicclsm alignment.
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2023-11-10 18:26:55 -06:00 |
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Rose Thompson
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02ab9fe99c
|
Fixed all the bugs associated with the signature and the store side of misaligned access. Load misaligned is still causing some issues.
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2023-11-10 17:58:42 -06:00 |
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Rose Thompson
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bd866e1025
|
Fixed some more bugs in the Zicclsm signature.
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2023-11-10 17:36:10 -06:00 |
|
Rose Thompson
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efecb0c346
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Fixed bug in the Zicclsm test.
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2023-11-10 17:34:23 -06:00 |
|
Rose Thompson
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ada354f443
|
Fixed bug in the misaligned access test.
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2023-11-10 17:02:15 -06:00 |
|
Rose Thompson
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b74bfbeefd
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Merge branch 'main' into Zicclsm
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2023-11-10 16:15:32 -06:00 |
|
naichewa
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d67badfc60
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fix hardware interlock, hold mode deassert
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2023-11-08 15:20:51 -08:00 |
|
naichewa
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a5837eb62c
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fifo fixes and edge case testing
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2023-11-07 17:59:46 -08:00 |
|
naichewa
|
4651b807ed
|
added test cases
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2023-11-02 15:43:08 -07:00 |
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Rose Thompson
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0a4ed5515b
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Merge branch 'main' into Zicclsm
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2023-11-02 12:55:51 -05:00 |
|
Rose Thompson
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afa1d85e3b
|
Doesn't yet fully work.
Thomas is going to finish debugging while I'm on the RISCV summit next week.
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2023-11-02 12:07:42 -05:00 |
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Rose Thompson
|
7ba891f607
|
Progress. I think the remaining bugs are in the regression test's signature.
|
2023-11-01 17:51:48 -05:00 |
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naichewa
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9aa8a7af3e
|
comments, more test cases
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2023-11-01 01:26:34 -07:00 |
|
Rose Thompson
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5660eff57d
|
Working through issues with the psill logic.
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2023-10-31 18:50:13 -05:00 |
|
Rose Thompson
|
4984b3935f
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Progress
|
2023-10-31 14:50:33 -05:00 |
|
Rose Thompson
|
5ca428d6a8
|
Fixed bugs in misaligned test.
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2023-10-31 12:49:35 -05:00 |
|
Rose Thompson
|
c061440141
|
First stab at the misaligned test.
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2023-10-31 12:30:10 -05:00 |
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naichewa
|
7dd3f24d6c
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Merge branch 'main' into spi
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2023-10-30 17:01:41 -07:00 |
|
naichewa
|
2330f4ee63
|
hardware interlock
|
2023-10-30 17:00:20 -07:00 |
|
Rose Thompson
|
2241976d29
|
Updated mmu to not generate trap on cacheable misaligned access when supported.
Updated tests with David's help.
|
2023-10-30 18:26:11 -05:00 |
|
David Harris
|
f6a7f707bd
|
Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder.
|
2023-10-30 09:56:17 -07:00 |
|
Rose Thompson
|
0fd5b3b2ce
|
Updated comments in the cboz tests.
|
2023-10-20 15:15:47 -05:00 |
|
Rose Thompson
|
5a4028064a
|
Updated comments for the cbom tests.
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2023-10-20 15:13:52 -05:00 |
|
naichewa
|
0ff9ce527d
|
Merge branch 'main' into spi
|
2023-10-16 22:59:50 -07:00 |
|
David Harris
|
ac4216b43d
|
Incorporated new AMO tests from riscv-arch-test
|
2023-10-16 10:25:45 -07:00 |
|
David Harris
|
6245748ed7
|
Added CSR permission tests for mconfigptr, menvcfg, mseccfg, etc.
|
2023-10-15 15:31:03 -07:00 |
|
David Harris
|
b4891d88db
|
Added WALLY minfo test for rv32
|
2023-10-15 06:48:22 -07:00 |
|
David Harris
|
434d6b2c5c
|
minfo test working again with mconfigptr for RV64
|
2023-10-15 06:41:52 -07:00 |
|
naichewa
|
aa5abfc8e8
|
always working after reg bit swizzle changes
|
2023-10-13 14:22:32 -07:00 |
|
naichewa
|
f231c3d3a3
|
correct delay0, fmt register test entries
|
2023-10-12 15:13:23 -07:00 |
|
naichewa
|
d5d4f9d044
|
transferred spi changes in ECA-authorized commit
|
2023-10-12 13:36:57 -07:00 |
|
David Harris
|
d526d28804
|
Added MENVCFG.HADE bit and updated SVADU to depend on this bit
|
2023-10-04 09:34:28 -07:00 |
|
Ross Thompson
|
12c3c98824
|
Extended the CBOM test to cover a 4 way set associative cache with 4KiB ways.
|
2023-08-30 11:29:44 -05:00 |
|
David Harris
|
8d3ff59673
|
Completed basic tests of svnapot and svpbmt
|
2023-08-28 06:57:35 -07:00 |
|
Ross Thompson
|
cd3349bd26
|
Added rv32 cboz test.
|
2023-08-24 17:02:53 -05:00 |
|
Ross Thompson
|
914b6f9734
|
Now have CBOZ instructions working!
|
2023-08-24 16:47:35 -05:00 |
|
Ross Thompson
|
7d51690b7c
|
Oups forgot to include the 32-bit cbom test in previous commit.
|
2023-08-24 09:04:41 -05:00 |
|
Ross Thompson
|
310b700550
|
Have a working 32 bit cbom test!
|
2023-08-21 13:46:09 -05:00 |
|
Ross Thompson
|
d4c6ba627d
|
Working CBO tests for 64 bit!
|
2023-08-21 12:55:07 -05:00 |
|
Ross Thompson
|
5ed096e4bc
|
Made a bunch of progress towards getting cbo instructions tested.
|
2023-08-21 11:46:21 -05:00 |
|
David Harris
|
c137a1c8cf
|
Fixed timer interrupt testing
|
2023-06-09 17:20:41 -07:00 |
|
David Harris
|
f68b9c224a
|
Fixed WALLY-trap test case to use menvcfg
|
2023-06-09 15:24:26 -07:00 |
|
David Harris
|
b70b0c7c5e
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Added support for menvcfg and senvcfg, including menvcfg.STCE for supervisor timer compare
|
2023-06-09 14:40:01 -07:00 |
|
David Harris
|
19096a812a
|
Added Zifencei ISA to tests where necessary to support new compiler
|
2023-05-16 11:18:27 -07:00 |
|
David Harris
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0a7a159d69
|
Added Zicsr and zifencei to RVTEST_ISA in custom tests where necessary to make them compile
|
2023-05-14 06:58:29 -07:00 |
|
Kip Macsai-Goren
|
34200e8c76
|
restored original virt mem tests when svadu is not supported
|
2023-04-11 18:47:08 -07:00 |
|
Kip Macsai-Goren
|
c4766c8a02
|
renamed virt mem tests to include svadu
|
2023-04-11 18:46:37 -07:00 |
|
Kip Macsai-Goren
|
b2d6084eea
|
removed unnecessary 'deadbeef's at the end of reference outputs
|
2023-04-11 18:32:04 -07:00 |
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Kip Macsai-Goren
|
a82c0a7780
|
Modified virt mem tests to do correct r/w when svadu is enabled
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2023-04-11 18:08:30 -07:00 |
|
Kip Macsai-Goren
|
e0b938b409
|
Removed Trap outputs from writes covered by SVADU
|
2023-04-11 17:41:57 -07:00 |
|
Kip Macsai-Goren
|
a899606c2b
|
Removed Sail from virt mem tests due to sail not recognizing SVADU
|
2023-04-11 17:41:31 -07:00 |
|
Kip Macsai-Goren
|
19305fe60a
|
Added sail simulation to priv tests that support it
|
2023-04-11 13:26:59 -07:00 |
|
Kip Macsai-Goren
|
a7c9d3d37b
|
ported medelg fixes to 32 bit tests. Requires a make allclean
|
2023-03-29 16:31:28 -07:00 |
|
Kip Macsai-Goren
|
2e151b6b08
|
updated tests to reflect non-writeable bits of deleg
|
2023-03-29 15:24:00 -07:00 |
|
David Harris
|
2e5c50e24a
|
Fixed RV32 tests after PMP fix
|
2023-03-28 08:35:23 -07:00 |
|
David Harris
|
e8904411ce
|
Fixed PMP issue 132. Updated tests to initialize PMP before using. Needs to remake tests
|
2023-03-28 06:58:17 -07:00 |
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Kip Macsai-Goren
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106ed02a7e
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Revert "added premilinary boundary ccrossing cases"
This reverts commit 7870148814.
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2023-03-24 11:27:41 -07:00 |
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Kip Macsai-Goren
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758da62a9f
|
ported fixes to 32 bit tests
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2023-03-24 11:22:39 -07:00 |
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Kip Macsai-Goren
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ff59fefcc9
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replaced inerrupt tests with allowed versions
|
2023-03-24 11:22:39 -07:00 |
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Kip Macsai-Goren
|
6f15ae1225
|
Added cause_s_soft_from_m_interrupt
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2023-03-24 11:22:39 -07:00 |
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Kip Macsai-Goren
|
7870148814
|
added premilinary boundary ccrossing cases
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2023-03-24 11:22:39 -07:00 |
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Kip Macsai-Goren
|
db6caedfec
|
added in the CSR name for stimecmp(h)
|
2023-03-04 15:53:03 -08:00 |
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Kip Macsai-Goren
|
ab6b953a4b
|
removed changes to counteren from stimecmp tests
|
2023-03-04 15:46:57 -08:00 |
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Kip Macsai-Goren
|
ac5c53a870
|
Added correct causing and handling of S time interrupts to test suite.
|
2023-03-04 15:04:17 -08:00 |
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David Harris
|
f0c0111ab0
|
Renamed section 12.3 to 8.3 in MMU test definitions
|
2023-02-19 05:46:46 -08:00 |
|
David Harris
|
4883351bd2
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
|
2023-01-28 18:18:53 -08:00 |
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Kip Macsai-Goren
|
ee1bcf62ee
|
Fixed regression test dependance on bp status by adding handling of UART tx empty interrupts.
|
2023-01-28 17:29:35 -08:00 |
|
David Harris
|
cea89f27cf
|
Removed unused WALLY test references
|
2023-01-27 07:25:04 -08:00 |
|
David Harris
|
2af94bf283
|
Removed unused reference files
|
2023-01-27 07:21:55 -08:00 |
|
Kip Macsai-Goren
|
964084f0b3
|
added fs=00 to status fp enabled test
|
2022-12-22 15:15:53 -08:00 |
|
Kip Macsai-Goren
|
d25d699800
|
Added status.tvm bit test that passes make and regression
|
2022-12-22 14:43:22 -08:00 |
|
Kip Macsai-Goren
|
a37bde7452
|
updated trap handler alignemnts to 64 bytes in priv tests
|
2022-12-22 14:23:04 -08:00 |
|
David Harris
|
ca949f2110
|
Only delegated bits of SIP are readable
|
2022-12-21 12:32:49 -08:00 |
|
Ross Thompson
|
f6393d1288
|
Waiting on fix for wally64periph uart test.
would like to remove vectored interrupt adder.
|
2022-12-21 13:16:09 -06:00 |
|
Ross Thompson
|
c41d58bd29
|
Vectored interrupts now require 64 byte alignment.
Eliminates adder.
|
2022-12-21 12:05:49 -06:00 |
|
Kip Macsai-Goren
|
55627f40e2
|
added passing GPIO test to 64 bit tests
|
2022-12-05 21:31:00 -08:00 |
|
Kip Macsai-Goren
|
4c81b6fa5f
|
added corrrect scr read out of uart to periph test
|
2022-12-05 20:16:02 -08:00 |
|
Kip Macsai-Goren
|
4ab99904a4
|
added all 32 bit tests to 64 bit periph tests except gpio
|
2022-12-05 20:16:02 -08:00 |
|
Kip Macsai-Goren
|
51e78d9e48
|
added copies of 64 bit tests to 32 bit periph and priv tests
|
2022-12-05 20:16:02 -08:00 |
|
Kip Macsai-Goren
|
540d6c2f41
|
added -01 to all WALLY tests
|
2022-12-05 20:16:02 -08:00 |
|
Kip Macsai-Goren
|
9b1765ce92
|
added tests for invalid address being written to satp. Not passing regression
|
2022-11-27 13:22:35 -08:00 |
|
Kip Macsai-Goren
|
21e045eb7d
|
added potential fix to overrun error and fifo interrupt error. test passes
|
2022-11-06 22:01:02 -08:00 |
|
Kip Macsai-Goren
|
90ef371abc
|
fixed fifo timout handling. error now in data ready interrupt
|
2022-11-05 13:34:24 -07:00 |
|
Kip Macsai-Goren
|
c06da6e6fe
|
fixed broken instructions so make works.
|
2022-11-03 23:06:20 +00:00 |
|
Ross Thompson
|
103514a8e0
|
More outline for uart timeout interrupt.
|
2022-10-28 13:53:56 -05:00 |
|
Ross Thompson
|
21eca47d2e
|
Untested change to uart test for outline of how to handle rx fifo timeout.
|
2022-10-28 13:31:16 -05:00 |
|
Kip Macsai-Goren
|
6e45698b86
|
Added test for UART FIFO timeout. Does not pass regression
|
2022-10-25 05:35:56 +00:00 |
|
Kip Macsai-Goren
|
c18c181fc0
|
fixed endianness mstatush problem, passes make, not regression
|
2022-10-04 17:37:39 +00:00 |
|
Kip Macsai-Goren
|
e603973dff
|
added xlen and endianness test edits. xlen passes but endinanness still won't make
|
2022-09-26 05:03:19 +00:00 |
|
Kip Macsai-Goren
|
9821a50eaa
|
added mstatus uxl, sxl bit tests (not tested in regression yet)
|
2022-09-18 00:11:29 +00:00 |
|
Kip Macsai-Goren
|
0cc7f5719c
|
ported endianness tests to 32 bits (not tested in regression yet)
|
2022-09-18 00:10:29 +00:00 |
|
Kip Macsai-Goren
|
c5cbe43732
|
Fixed typos in existing endianness test
|
2022-09-18 00:09:52 +00:00 |
|
Kip Macsai-Goren
|
e6987524ab
|
added full coverage of subword loads and stores to endianness test
|
2022-09-17 23:14:38 +00:00 |
|
Kip Macsai-Goren
|
cc7d1c8ef9
|
Created initial endianness tests
|
2022-09-16 01:06:26 +00:00 |
|
David Harris
|
898dbc8e74
|
Completed PLIC-S tests. Regression working. This completes peripheral tests.
|
2022-08-03 09:33:56 -07:00 |
|
David Harris
|
4fb467ee8a
|
Debugging plic-s test
|
2022-08-03 13:21:09 +00:00 |
|
David Harris
|
7e5b78f240
|
plic-s debug
|
2022-08-03 12:33:09 +00:00 |
|
David Harris
|
cab0349701
|
Started plic-s tests
|
2022-08-03 03:48:08 +00:00 |
|
David Harris
|
93d7d7179e
|
Added parity and stop bit tests to UART
|
2022-07-28 04:35:51 +00:00 |
|
David Harris
|
429bdae1c4
|
Fixed UART reference output
|
2022-07-27 22:16:38 +00:00 |
|