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366 Commits

Author SHA1 Message Date
bbracker
d85da77069 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-17 14:46:38 -04:00
bbracker
ac908bc2e4 swapped out linux testbench signal names 2021-07-17 14:46:18 -04:00
David Harris
9741b01465 hptw: minor cleanup 2021-07-17 13:40:12 -04:00
Ross Thompson
abce241f68 Also changed the shadow ram's dcache copy widths. 
Merge branch 'dcache' into main
 2021-07-16 14:21:09 -05:00
Ross Thompson
bebc7cc5e3 Updated wave file. 2021-07-16 12:34:37 -05:00
Ross Thompson
d3715acf2d Fixed walker fault interaction with dcache. 2021-07-16 12:22:13 -05:00
bbracker
d38109bc1c changed stop of linux boot from arch_cpu_idle to do_idle 2021-07-16 12:27:15 -04:00
Ross Thompson
96aa106852 Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault. 2021-07-15 11:56:35 -05:00
Ross Thompson
4549a9f1c9 Merge branch 'main' into dcache 2021-07-15 11:55:20 -05:00
Ross Thompson
5fb5ac3d5a Updated wave file. 2021-07-15 11:04:49 -05:00
Ross Thompson
f234875779 dcache STATE_CPU_BUSY needs to assert CommittedM. This is required to ensure a completed memory operation is not bound to an interrupt. ie. MEPC should not be PCM when committed. 2021-07-14 23:08:07 -05:00
Ross Thompson
6163629204 Finally have the ptw correctly walking through the dcache to update the itlb. 
Still not working fully.
 2021-07-14 22:26:07 -05:00
Katherine Parry
701ea38964 Fixed lint warning 2021-07-14 21:24:48 -04:00
Ross Thompson
d3a1a2c90a Fixed d cache not honoring StallW for uncache writes and reads. 2021-07-14 17:23:28 -05:00
Ross Thompson
771c7ff130 Routed CommittedM and PendingInterruptM through the lsu arb. 2021-07-14 16:18:09 -05:00
Ross Thompson
ef598d0e79 Implemented uncached reads. 2021-07-13 23:03:09 -05:00
Ross Thompson
278bbfbe3c Partially working changes to support uncached memory access. Not sure what CommitedM is. 2021-07-13 17:24:59 -05:00
Ross Thompson
b780e471b4 Fixed interaction between icache stall and dcache. On hit dcache needs to enter a cpu busy state when the cpu is stalled. 2021-07-13 14:51:42 -05:00
Ross Thompson
51249a0e04 Fixed the fetch buffer accidental overwrite on eviction. 2021-07-13 14:21:29 -05:00
Ross Thompson
2034a6584f Dcache AHB address generation was wrong. Needed to zero the offset. 2021-07-13 14:19:04 -05:00
Ross Thompson
ee09fa5f58 Moved StoreStall into the hazard unit instead of in the d cache. 2021-07-13 13:20:50 -05:00
David Harris
516b710db6 Fixed busybear by restoring InstrValidW needed by testbench 2021-07-13 14:17:36 -04:00
Katherine Parry
acdd2e4504 Fixed writting MStatus FS bits 2021-07-13 13:20:30 -04:00
Ross Thompson
17dc488010 Got the shadow ram cache flush working. 2021-07-13 10:03:47 -05:00
Ross Thompson
9fe6190763 Team work on solving the dcache data inconsistency problem. 2021-07-12 23:46:32 -05:00
Ross Thompson
8ca8b9075d Progress towards the test bench flush. 2021-07-12 14:22:13 -05:00
Katherine Parry
0cc07fda1b Almost all convert instructions pass Imperas tests 2021-07-11 18:06:33 -04:00
Ross Thompson
a82c4c99c2 Actually writes the correct data now on stores. 2021-07-10 17:48:47 -05:00
Ross Thompson
71a23626d5 Fixed bug in the LSU pagetable walker interlock. 2021-07-06 10:41:36 -05:00
Ross Thompson
59913e13aa Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-05 16:07:27 -05:00
David Harris
e65fb5bb35 Added F_SUPPORTED flag to disable floating point unit when not in MISA 2021-07-05 10:30:46 -04:00
Ross Thompson
f2c4df0a5b Removed the TranslationVAdrQ as it is not necessary. 2021-07-04 16:49:34 -05:00
Ross Thompson
8e48865140 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-04 16:19:39 -05:00
Ross Thompson
8ae0a5bd7d relocated lsuarb and pagetable walker inside the lsu. Does not pass busybear or buildroot, but passes rv32ic and rv64ic. 2021-07-04 13:49:38 -05:00
David Harris
c897bef8cd Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang. 2021-07-04 01:19:38 -04:00
Ben Bracker
9709bd78e1 stop busybear from hanging 2021-07-02 17:22:09 -05:00
Ross Thompson
549b7b2a62 Merge branch 'main' into bigbadbranch 2021-07-02 11:52:26 -05:00
Ross Thompson
3dae02818c OMG. It's working! 2021-07-01 17:37:53 -05:00
Ross Thompson
c3eaa3169e Fixed the wrong virtual address write into the dtlb. 2021-07-01 16:55:16 -05:00
Ross Thompson
9d9415ea67 Got some stores working in virtual memory. 2021-07-01 12:49:09 -05:00
Ross Thompson
4530e43df6 The icache ptw interlock is actually correct now. There needed to be a 1 cycle delay. 2021-06-30 17:02:36 -05:00
Ross Thompson
07a0b66fdf Major rewrite of ptw to remove combo loop. 2021-06-30 16:25:03 -05:00
Ross Thompson
b31e0afc2a The icache now correctly interlocks with the PTW on TLB miss. 2021-06-30 11:24:26 -05:00
Ross Thompson
2598f08782 Page table walker now walks the table. 
Added interlock so the icache stalls.
Page table walker not walking correctly, goes to fault state.
 2021-06-29 22:33:57 -05:00
Ross Thompson
ae6140bd94 Don't use this branch walker still broken. 2021-06-28 17:26:11 -05:00
Ross Thompson
8dfbf60b67 AMO and LR/SC instructions now working correctly. 
Page table walking is not working.
 2021-06-25 15:42:07 -05:00
Ross Thompson
9fd1761fd6 Working through a combo loop. 2021-06-25 14:49:27 -05:00
Ross Thompson
17636b3293 Regression test runs further. The LSU state machine which fakes the Dcache had a few bugs. MemAccessM needed to be squashed on bus faults. 2021-06-25 11:05:17 -05:00
bbracker
9927f771cc linux testbench now ignores HWRITE glitches caused by flush glitches 2021-06-25 09:28:52 -04:00
Ross Thompson
d8183e59e4 Works until pma checker breaks the simulation by reading HADDR rather than data physical address. 2021-06-24 14:42:59 -05:00
bbracker
3d6b422e34 regression can overcome the fact that buildroots UART prints stuff 2021-06-24 02:00:01 -04:00
bbracker
409a73604c whoops meant to remove notifications from busybear, not buildroot 2021-06-24 01:54:46 -04:00
bbracker
b84419ff4e overhauled linux testbench and spoofed MTTIME interrupt 2021-06-24 01:42:35 -04:00
David Harris
718630c378 Reduced complexity of pmpadrdec 2021-06-23 03:03:52 -04:00
bbracker
56b0d4d016 added slack notifier for long sims 2021-06-22 08:31:41 -04:00
bbracker
1f2a967e0f read from MSTATUS workaround because QEMU has incorrect MSTATUS 2021-06-20 10:11:39 -04:00
bbracker
6e9c6e3e6a whoops wavedo typo 2021-06-20 05:36:54 -04:00
bbracker
9469367da3 make buildroot ignore SSTATUS because QEMU did not originally log it 2021-06-20 05:31:24 -04:00
bbracker
52fb630379 remove lingering busybear stuff from buildroot do files 2021-06-20 00:50:53 -04:00
bbracker
3e32ba3684 make buildroot waves only turn on after a user-specified point 2021-06-20 00:39:30 -04:00
David Harris
43bc17350b Restored wally-busybear testbench now that graphical sim is working 2021-06-18 12:36:25 -04:00
bbracker
72f1e3eab6 buildroot added to regression because it passes regression 2021-06-18 09:49:30 -04:00
David Harris
e03912f64c Cleaned up name of MTIME register in CSRC 2021-06-18 07:53:49 -04:00
bbracker
832e4fc7e3 making linux waveforms more useful 2021-06-17 08:37:37 -04:00
bbracker
3e11da2aa2 temporarily removing buildroot from regression until it is regenerated 2021-06-07 13:20:50 -04:00
David Harris
95cc70295b Merge difficulties 2021-06-07 09:50:23 -04:00
David Harris
8bbabb683d Refactored configuration files and renamed testbench-busybear to testbench-linux 2021-06-07 09:46:52 -04:00
Ross Thompson
6f58c66be8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-06-04 15:16:39 -05:00
Ross Thompson
e200b4b5a4 Continued I-Cache cleanup. 
Removed strange mux on InstrRawD along with
the select logic.
 2021-06-04 15:14:05 -05:00
Ross Thompson
35afdecda2 Moved I-Cache offset selection mux to icache.sv (top level). 
When we switch to set associative this is will be more efficient.
 2021-06-04 13:49:33 -05:00
Katherine Parry
19116ed889 Double-precision FMA instructions 2021-06-04 14:00:11 -04:00
Ross Thompson
2c16591396 Reorganized the icache names. 2021-06-04 12:53:42 -05:00
David Harris
a61411995a moved shared constants to a shared directory 2021-06-03 22:41:30 -04:00
bbracker
8338b3bd34 expanded GPIO testing and caught small GPIO bug 2021-06-03 10:03:09 -04:00
bbracker
28abd28b1f fixed InstrValid signals and implemented less costly MEPC loading 2021-06-02 10:03:19 -04:00
bbracker
a45b61ede9 turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\) 2021-05-28 23:11:37 -04:00
bbracker
142b02b30a improved PLIC test organization 2021-05-21 15:13:02 -04:00
Katherine Parry
71e4a10efb FMV.D.X imperas test passes 2021-05-20 22:17:59 -04:00
bbracker
114bba8370 small bit of busybear debug progress 2021-05-19 20:18:00 -04:00
James E. Stine
058b265d18 Update rv64icfd batch script 2021-05-18 16:01:53 -05:00
David Harris
5f214d60b6 Removed rv64wally 2021-05-18 14:08:46 -04:00
David Harris
433ea61d9e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/regression/vish_stacktrace.vstf
 2021-05-18 14:01:19 -04:00
bbracker
86d55cd07a fixed busybear floating point NOP-out feature; restored regression to check 100000 instructions 2021-05-17 19:25:54 -04:00
bbracker
69ef758e78 regression modified to timeout after 10 min \n took Harris\' suggestion for avoiding using ahbliteState package in busybear testbench 2021-05-17 18:44:47 -04:00
David Harris
1aa1908994 Deleted vish_stacktrace 2021-05-17 18:39:01 -04:00
Elizabeth Hedenberg
853c9243c1 commit ehedenberg coremark 2021-05-17 18:02:35 -04:00
James E. Stine
8822bdd6ad Cleanup of regression 2021-05-17 16:58:15 -05:00
James E. Stine
97cbdae674 Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version 2021-05-17 16:48:51 -05:00
Thomas Fleming
a191978a97 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-14 07:40:08 -04:00
Thomas Fleming
1fc607b399 Remove busy-mmu and fix missing signal 2021-05-14 07:14:20 -04:00
Jarred Allen
dc41623754 Minor fixes in regression 2021-05-09 13:57:09 -04:00
Jarred Allen
788680fa4d Fix bug in regression script 2021-05-06 12:56:57 -04:00
Jarred Allen
15da77fe15 Clean up regression script and document it 2021-05-04 18:58:59 -04:00
Thomas Fleming
d53afc8510 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-03 23:15:39 -04:00
Elizabeth Hedenberg
08bfaeffe3 coremark print statment 2021-05-03 19:35:08 -04:00
Elizabeth Hedenberg
81ed9b5d06 coremark directory changes 2021-05-03 19:35:06 -04:00
Ross Thompson
21c0ee0cf2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-03 16:56:00 -05:00
Ross Thompson
ed4f2ecb24 fixed subtle typo in icache fsm. Was messing up hit spill hit. 
I believe the mibench qsort benchmark runs after this icache fix.
 2021-05-03 16:55:36 -05:00
Thomas Fleming
3f7061d557 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-03 17:38:13 -04:00
Jarred Allen
a21b84e2ad Add lint to regression 2021-05-03 17:32:05 -04:00