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wave-dos
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fixed InstrValid signals and implemented less costly MEPC loading
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2021-06-02 10:03:19 -04:00 |
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regression-wally.py
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fixed busybear floating point NOP-out feature; restored regression to check 100000 instructions
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2021-05-17 19:25:54 -04:00 |
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run_sim.sh
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-03-30 15:25:07 -04:00 |
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sim-buildroot
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start to add buildroot testbench
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2021-04-16 23:27:29 -04:00 |
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sim-buildroot-batch
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start to add buildroot testbench
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2021-04-16 23:27:29 -04:00 |
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sim-busybear
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busybear: add sim-busybear and sim-busybear-batch based on sim-wally
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2021-03-01 21:01:15 +00:00 |
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sim-busybear-batch
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busybear: make a second .do file with better optimization for command line mode
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2021-03-08 19:35:00 +00:00 |
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sim-wally
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sim-wally-batch
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Fixed issue with sim-wally-batch. Are people still using this script?
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2021-03-17 11:17:52 -05:00 |
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sim-wally-batch-muldiv
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Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version
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2021-05-17 16:48:51 -05:00 |
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sim-wally-batch-rv32ic
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fixed sim-wally-32ic
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2021-04-08 13:40:16 -04:00 |
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sim-wally-batch-rv64icfd
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Update rv64icfd batch script
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2021-05-18 16:01:53 -05:00 |
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sim-wally-muldiv
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Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version
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2021-05-17 16:48:51 -05:00 |
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sim-wally-rv32ic
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fixed sim-wally-32ic
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2021-04-08 13:40:16 -04:00 |
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udiv.c
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Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version
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2021-05-17 16:48:51 -05:00 |
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wally-buildroot-batch.do
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do script refactor
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2021-04-24 09:32:09 -04:00 |
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wally-buildroot.do
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do script refactor
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2021-04-24 09:32:09 -04:00 |
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wally-busybear-batch.do
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Minor fixes in regression
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2021-05-09 13:57:09 -04:00 |
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wally-busybear.do
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small bit of busybear debug progress
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2021-05-19 20:18:00 -04:00 |
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wally-coremark_bare.do
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coremark print statment
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2021-05-03 19:35:08 -04:00 |
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wally-pipelined-batch-muldiv.do
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Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version
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2021-05-17 16:48:51 -05:00 |
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wally-pipelined-batch-rv64icfd.do
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Update rv64icfd batch script
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2021-05-18 16:01:53 -05:00 |
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wally-pipelined-batch.do
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Condense the parallel and non-parallel wally-pipelined-batch.do files into one
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2021-03-16 18:15:13 -04:00 |
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wally-pipelined-muldiv.do
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Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version
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2021-05-17 16:48:51 -05:00 |
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wally-pipelined-ross.do
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Converted branch predictor preloads to use system verilog rather than modelsim's load command.
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2021-03-15 12:39:44 -05:00 |
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wally-pipelined.do
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turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
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2021-05-28 23:11:37 -04:00 |
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wally-privileged.do
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Add medeleg tests
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2021-04-29 15:02:36 -04:00 |
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wave-all.do
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-03-30 15:25:07 -04:00 |
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wave.do
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fixed subtle typo in icache fsm. Was messing up hit spill hit.
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2021-05-03 16:55:36 -05:00 |
