mirror of
https://github.com/openhwgroup/cvw
synced 2025-01-30 16:34:28 +00:00
Removed rv64wally
This commit is contained in:
David Harris
commit
5f214d60b6
1
.gitignore
vendored
1
.gitignore
vendored
@ -15,6 +15,7 @@ wlft*
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/imperas-riscv-tests/FunctionRadix_64.addr
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/imperas-riscv-tests/FunctionRadix.addr
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/imperas-riscv-tests/ProgramMap.txt
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/imperas-riscv-tests/logs
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/wally-pipelined/busybear-testgen/gdbcombined.txt
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/wally-pipelined/busybear-testgen/first10.txt
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*.o
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@ -31,7 +31,7 @@
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`define XLEN 64
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//`define MISA (32'h00000105)
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`define MISA (32'h00000104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12 | 1 << 0)
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`define MISA (32'h00000104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12 | 1 << 0 | 1 << 3)
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`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
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`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
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`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
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@ -26,7 +26,7 @@ configs = [
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TestCase(
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name="busybear",
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cmd="vsim -do wally-busybear-batch.do -c > {}",
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grepstr="# loaded 40000 instructions"
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grepstr="# loaded 100000 instructions"
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),
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TestCase(
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name="buildroot",
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@ -50,37 +50,50 @@ configs = [
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),
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]
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import multiprocessing, os
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import os
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from multiprocessing import Pool, TimeoutError
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def search_log_for_text(text, logfile):
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"""Search through the given log file for text, returning True if it is found or False if it is not"""
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grepcmd = "grep -e '%s' '%s' > /dev/null" % (text, logfile)
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return os.system(grepcmd) == 0
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def run_test_case(case):
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def run_test_case(config):
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"""Run the given test case, and return 0 if the test suceeds and 1 if it fails"""
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logname = "regression_logs/wally_"+case.name+".log"
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cmd = case.cmd.format(logname)
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logname = "regression_logs/wally_"+config.name+".log"
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cmd = config.cmd.format(logname)
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print(cmd)
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os.system(cmd)
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if search_log_for_text(case.grepstr, logname):
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print("%s: Success" % logname)
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if search_log_for_text(config.grepstr, logname):
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print("%s: Success" % config.name)
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return 0
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else:
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print("%s: failures detected" % logname)
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print("%s: Failures detected in output" % config.name)
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print(" Check %s" % logname)
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return 1
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def main():
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"""Run the tests and count the failures"""
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# Scale the number of concurrent processes to the number of test cases, but
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# max out at 12 concurrent processes to not overwhelm the system
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TIMEOUT_DUR = 600 # seconds
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try:
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os.mkdir("regression_logs")
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except:
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pass
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pool = multiprocessing.Pool(min(len(configs), 12))
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with Pool(processes=min(len(configs),12)) as pool:
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num_fail = 0
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results = {}
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for config in configs:
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results[config] = pool.apply_async(run_test_case,(config,))
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for (config,result) in results.items():
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try:
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num_fail+=result.get(timeout=TIMEOUT_DUR)
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except TimeoutError:
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num_fail+=1
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print("%s: Timeout - runtime exceeded %d seconds" % (config.name, TIMEOUT_DUR))
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# Count the number of failures
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num_fail = sum(pool.map(run_test_case, configs))
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if num_fail:
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print("Regression failed with %s failed configurations" % num_fail)
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# Remind the user to try `make allclean`, since it may be needed if test
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@ -36,7 +36,7 @@ vopt +acc work.testbench -o workopt
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vsim workopt -suppress 8852,12070
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#do ./wave-dos/peripheral-waves.do
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do ./wave-dos/busybear-waves.do
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do ./wave-dos/default-waves.do
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#do busy-mmu.do
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@ -200,7 +200,7 @@ module fctrl (
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// fmv.d.w = ?101
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// {?, is mv, is store, is double or fcvt.d.w}
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3'b111 : OpCtrlD = {1'b0, OpD[6:5], Funct3D[0] | (OpD[6]&Funct7D[0])};
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default : begin OpCtrlD = 4'bxxxx; IllegalFPUInstrD = isFP; end
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default : begin OpCtrlD = 4'bxxxx; IllegalFPUInstrD = 1'b1; end
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endcase
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end
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@ -48,9 +48,9 @@ module fpu (
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localparam PipeEnable = 1'b1;
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always_comb begin
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PipeEnableDE = StallE;
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PipeEnableEM = StallM;
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PipeEnableMW = StallW;
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PipeEnableDE = ~StallE;
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PipeEnableEM = ~StallM;
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PipeEnableMW = ~StallW;
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PipeClearDE = FlushE;
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PipeClearEM = FlushM;
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PipeClearMW = FlushW;
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@ -47,7 +47,7 @@ module privdec (
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assign wfiM = PrivilegedM & (InstrM[31:20] == 12'b000100000101);
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assign sfencevmaM = PrivilegedM & (InstrM[31:25] == 7'b0001001);
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assign IllegalPrivilegedInstrM = PrivilegedM & ~(uretM|sretM|mretM|ecallM|ebreakM|wfiM|sfencevmaM);
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assign IllegalInstrFaultM = IllegalIEUInstrFaultM | IllegalFPUInstrM | IllegalPrivilegedInstrM | IllegalCSRAccessM | IllegalFPUInstrM; // *** generalize this for other instructions
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assign IllegalInstrFaultM = (IllegalIEUInstrFaultM & IllegalFPUInstrM) | IllegalPrivilegedInstrM | IllegalCSRAccessM; // *** generalize this for other instructions
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// *** initially, wfi and sfencevma are nop
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// *** zfenci extension?
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@ -52,6 +52,7 @@ module privileged (
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input logic TimerIntM, ExtIntM, SwIntM,
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input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM,
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input logic [4:0] SetFflagsM,
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output logic IllegalFPUInstrE,
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output logic [1:0] PrivilegeModeW,
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output logic [`XLEN-1:0] SATP_REGW,
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output logic STATUS_MXR, STATUS_SUM,
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@ -78,7 +79,7 @@ module privileged (
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logic uretM, sretM, mretM, ecallM, ebreakM, wfiM, sfencevmaM;
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logic IllegalCSRAccessM;
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logic IllegalIEUInstrFaultE, IllegalIEUInstrFaultM;
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logic IllegalFPUInstrE, IllegalFPUInstrM;
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logic IllegalFPUInstrM;
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logic LoadPageFaultM, StorePageFaultM;
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logic InstrPageFaultF, InstrPageFaultD, InstrPageFaultE, InstrPageFaultM;
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logic InstrAccessFaultF, InstrAccessFaultD, InstrAccessFaultE, InstrAccessFaultM;
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@ -96,7 +96,7 @@ module wallypipelinedhart (
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logic SquashSCW;
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logic [31:0] FSROutW;
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logic DivSqrtDoneE;
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logic IllegalFPUInstrD;
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logic IllegalFPUInstrD, IllegalFPUInstrE;
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logic [`XLEN-1:0] FPUResultW;
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// memory management unit signals
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@ -261,11 +261,10 @@ module testbench();
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logic [`XLEN-1:0] readAdrExpected, readAdrTranslated;
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import ahbliteState::*;
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always @(dut.HRDATA) begin
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#2;
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if (dut.hart.MemRWM[1]
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&& (dut.hart.ebu.BusState == MEMREAD || dut.hart.ebu.BusState == ATOMICREAD)
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&& (dut.hart.ebu.CaptureDataM)
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&& dut.HRDATA !== {64{1'bx}}) begin
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//$display("%0t", $time);
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if($feof(data_file_memR)) begin
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@ -469,12 +468,13 @@ module testbench();
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speculative = ~equal(dut.hart.ifu.PCD,pcExpected,3);
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if(dut.hart.ifu.PCD===pcExpected) begin
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if(dut.hart.ifu.InstrRawD[6:0] == 7'b1010011) begin // for now, NOP out any float instrs
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force CheckInstrD = 32'b0010011;
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release CheckInstrD;
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force dut.hart.ifu.InstrRawD = 32'b0010011;
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#7;
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release dut.hart.ifu.InstrRawD;
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$display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtext, dut.hart.ifu.PCD, instrs, $time);
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force CheckInstrD = 32'b0010011;
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force dut.hart.ifu.InstrRawD = 32'b0010011;
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while (clk != 0) #1;
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while (clk != 1) #1;
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release dut.hart.ifu.InstrRawD;
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release CheckInstrD;
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warningCount += 1;
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forcedInstr = 1;
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end
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@ -497,12 +497,13 @@ module testbench();
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scan_file_PC = $fscanf(data_file_PC, "%x\n", CheckInstrD);
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if(dut.hart.ifu.PCD === pcExpected) begin
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if(dut.hart.ifu.InstrRawD[6:0] == 7'b1010011) begin // for now, NOP out any float instrs
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force CheckInstrD = 32'b0010011;
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release CheckInstrD;
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force dut.hart.ifu.InstrRawD = 32'b0010011;
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#7;
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release dut.hart.ifu.InstrRawD;
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$display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtext, dut.hart.ifu.PCD, instrs, $time);
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force CheckInstrD = 32'b0010011;
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force dut.hart.ifu.InstrRawD = 32'b0010011;
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while (clk != 0) #1;
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while (clk != 1) #1;
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release dut.hart.ifu.InstrRawD;
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release CheckInstrD;
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warningCount += 1;
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forcedInstr = 1;
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end
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@ -52,11 +52,110 @@ module testbench();
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"rv64mmu/WALLY-VIRTUALMEMORY", "2000"
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};
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string tests32f[] = '{
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"rv32f/I-FADD-S-01", "2000",
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"rv32f/I-FCLASS-S-01", "2000",
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"rv32f/I-FCVT-S-L-01", "2000",
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"rv32f/I-FCVT-S-LU-01", "2000",
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"rv32f/I-FCVT-S-W-01", "2000",
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"rv32f/I-FCVT-S-WU-01", "2000",
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"rv32f/I-FCVT-L-S-01", "2000",
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"rv32f/I-FCVT-LU-S-01", "2000",
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"rv32f/I-FCVT-W-S-01", "2000",
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"rv32f/I-FCVT-WU-S-01", "2000",
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"rv32f/I-FDIV-S-01", "2000",
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"rv32f/I-FEQ-S-01", "2000",
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"rv32f/I-FLE-S-01", "2000",
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"rv32f/I-FLT-S-01", "2000",
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"rv32f/I-FMADD-S-01", "2000",
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"rv32f/I-FMAX-S-01", "2000",
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"rv32f/I-FMIN-S-01", "2000",
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"rv32f/I-FMSUB-S-01", "2000",
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"rv32f/I-FMUL-S-01", "2000",
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"rv32f/I-FMV-W-X-01", "2000",
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"rv32f/I-FMV-X-W-01", "2000",
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"rv32f/I-FNMADD-S-01", "2000",
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"rv32f/I-FNMSUB-S-01", "2000",
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"rv32f/I-FSGNJ-S-01", "2000",
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"rv32f/I-FSGNJN-S-01", "2000",
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"rv32f/I-FSGNJX-S-01", "2000",
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"rv32f/I-FSQRT-S-01", "2000",
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"rv32f/I-FSW-01", "2000",
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"rv32f/I-FLW-01", "2000",
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"rv32f/I-FSUB-S-01", "2000"
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};
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string tests64f[] = '{
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"rv64f/I-FADD-S-01", "2000",
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"rv64f/I-FCLASS-S-01", "2000"
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"rv64f/I-FCLASS-S-01", "2000",
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"rv64f/I-FCVT-S-L-01", "2000",
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"rv64f/I-FCVT-S-LU-01", "2000",
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"rv64f/I-FCVT-S-W-01", "2000",
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"rv64f/I-FCVT-S-WU-01", "2000",
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"rv64f/I-FCVT-L-S-01", "2000",
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"rv64f/I-FCVT-LU-S-01", "2000",
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"rv64f/I-FCVT-W-S-01", "2000",
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"rv64f/I-FCVT-WU-S-01", "2000",
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"rv64f/I-FDIV-S-01", "2000",
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"rv64f/I-FEQ-S-01", "2000",
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"rv64f/I-FLE-S-01", "2000",
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"rv64f/I-FLT-S-01", "2000",
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"rv64f/I-FMADD-S-01", "2000",
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"rv64f/I-FMAX-S-01", "2000",
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"rv64f/I-FMIN-S-01", "2000",
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"rv64f/I-FMSUB-S-01", "2000",
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"rv64f/I-FMUL-S-01", "2000",
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"rv64f/I-FMV-W-X-01", "2000",
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"rv64f/I-FNMADD-S-01", "2000",
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"rv64f/I-FNMSUB-S-01", "2000",
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"rv64f/I-FSGNJ-S-01", "2000",
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"rv64f/I-FSGNJN-S-01", "2000",
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"rv64f/I-FSGNJX-S-01", "2000",
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"rv64f/I-FSQRT-S-01", "2000",
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"rv64f/I-FSW-01", "2000",
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"rv64f/I-FLW-01", "2000",
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"rv64f/I-FSUB-S-01", "2000"
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};
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string tests64d[] = '{
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"rv64d/I-FMV-X-D-01", "2000",
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"rv64d/I-FADD-D-01", "2000",
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"rv64d/I-FCLASS-D-01", "2000",
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"rv64d/I-FCVT-D-L-01", "2000",
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"rv64d/I-FCVT-D-LU-01", "2000",
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"rv64d/I-FCVT-D-S-01", "2000",
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"rv64d/I-FCVT-D-W-01", "2000",
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"rv64d/I-FCVT-D-WU-01", "2000",
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"rv64d/I-FCVT-L-D-01", "2000",
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"rv64d/I-FCVT-LU-D-01", "2000",
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"rv64d/I-FCVT-S-D-01", "2000",
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"rv64d/I-FCVT-W-D-01", "2000",
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"rv64d/I-FCVT-WU-D-01", "2000",
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"rv64d/I-FDIV-D-01", "2000",
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"rv64d/I-FEQ-D-01", "2000",
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"rv64d/I-FLD-D-01", "2000",
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"rv64d/I-FLE-D-01", "2000",
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"rv64d/I-FLT-D-01", "2000",
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"rv64d/I-FMADD-D-01", "2000",
|
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"rv64d/I-FMAX-D-01", "2000",
|
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"rv64d/I-FMIN-D-01", "2000",
|
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"rv64d/I-FMSUB-D-01", "2000",
|
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"rv64d/I-FMUL-D-01", "2000",
|
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"rv64d/I-FMV-D-X-01", "2000",
|
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"rv64d/I-FNMADD-D-01", "2000",
|
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"rv64d/I-FNMSUB-D-01", "2000",
|
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"rv64d/I-FSD-01", "2000",
|
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"rv64d/I-FSGNJ-D-01", "2000",
|
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"rv64d/I-FSGNJN-D-01", "2000",
|
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"rv64d/I-FSGNJX-D-01", "2000",
|
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"rv64d/I-FSQRTD-01", "2000",
|
||||
"rv64d/I-FSUB-D-01", "2000"
|
||||
};
|
||||
|
||||
|
||||
|
||||
string tests64a[] = '{
|
||||
"rv64a/WALLY-AMO", "2110",
|
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"rv64a/WALLY-LRSC", "2110"
|
||||
@ -426,10 +525,10 @@ module testbench();
|
||||
if (`C_SUPPORTED) tests = {tests, tests64ic};
|
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else tests = {tests, tests64iNOc};
|
||||
if (`M_SUPPORTED) tests = {tests, tests64m};
|
||||
// if (`F_SUPPORTED) tests = {tests64f, tests};
|
||||
// if (`D_SUPPORTED) tests = {tests64d, tests};
|
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if (`A_SUPPORTED) tests = {tests, tests64a};
|
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if (`MEM_VIRTMEM) tests = {tests, tests64mmu};
|
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// if (`F_SUPPORTED) tests = {tests64f, tests};
|
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// if (`D_SUPPORTED) tests = {tests64d, tests};
|
||||
end
|
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//tests = {tests64a, tests};
|
||||
end else begin // RV32
|
||||
@ -555,6 +654,7 @@ module testbench();
|
||||
errors = errors+1;
|
||||
$display(" Error on test %s result %d: adr = %h sim = %h, signature = %h",
|
||||
tests[test], i, (testadr+i)*`XLEN/8, dut.uncore.dtim.RAM[testadr+i], signature[i]);
|
||||
// $stop;//***debug
|
||||
end
|
||||
end
|
||||
i = i + 1;
|
||||
@ -633,11 +733,13 @@ module instrNameDecTB(
|
||||
logic [2:0] funct3;
|
||||
logic [6:0] funct7;
|
||||
logic [11:0] imm;
|
||||
logic [4:0] rs2;
|
||||
|
||||
assign op = instr[6:0];
|
||||
assign funct3 = instr[14:12];
|
||||
assign funct7 = instr[31:25];
|
||||
assign imm = instr[31:20];
|
||||
assign rs2 = instr[24:20];
|
||||
|
||||
// it would be nice to add the operands to the name
|
||||
// create another variable called decoded
|
||||
@ -761,6 +863,67 @@ module instrNameDecTB(
|
||||
else if (funct7[6:2] == 5'b11100) name = "AMOMAXU.D";
|
||||
else name = "ILLEGAL";
|
||||
10'b0001111_???: name = "FENCE";
|
||||
10'b1000011_???: name = "FMADD";
|
||||
10'b1000111_???: name = "FMSUB";
|
||||
10'b1001011_???: name = "FNMSUB";
|
||||
10'b1001111_???: name = "FNMADD";
|
||||
10'b1010011_000: if (funct7[6:2] == 5'b00000) name = "FADD";
|
||||
else if (funct7[6:2] == 5'b00001) name = "FSUB";
|
||||
else if (funct7[6:2] == 5'b00010) name = "FMUL";
|
||||
else if (funct7[6:2] == 5'b00011) name = "FDIV";
|
||||
else if (funct7[6:2] == 5'b01011) name = "FSQRT";
|
||||
else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
|
||||
else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
|
||||
else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
|
||||
else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
|
||||
else if (funct7 == 7'b1110000 && rs2 == 5'b00000) name = "FMV.X.W";
|
||||
else if (funct7 == 7'b1111000 && rs2 == 5'b00000) name = "FMV.W.X";
|
||||
else if (funct7 == 7'b1110001 && rs2 == 5'b00000) name = "FMV.X.W"; // DOUBLE
|
||||
else if (funct7 == 7'b1111001 && rs2 == 5'b00000) name = "FMV.W.X"; // DOUBLE
|
||||
else if (funct7[6:2] == 5'b00100) name = "FSGNJ";
|
||||
else if (funct7[6:2] == 5'b00101) name = "FMIN";
|
||||
else if (funct7[6:2] == 5'b10100) name = "FLE";
|
||||
else name = "ILLEGAL";
|
||||
10'b1010011_001: if (funct7[6:2] == 5'b00000) name = "FADD";
|
||||
else if (funct7[6:2] == 5'b00001) name = "FSUB";
|
||||
else if (funct7[6:2] == 5'b00010) name = "FMUL";
|
||||
else if (funct7[6:2] == 5'b00011) name = "FDIV";
|
||||
else if (funct7[6:2] == 5'b01011) name = "FSQRT";
|
||||
else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
|
||||
else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
|
||||
else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
|
||||
else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
|
||||
else if (funct7[6:2] == 5'b00100) name = "FSGNJN";
|
||||
else if (funct7[6:2] == 5'b00101) name = "FMAX";
|
||||
else if (funct7[6:2] == 5'b10100) name = "FLT";
|
||||
else if (funct7[6:2] == 5'b11100) name = "FCLASS";
|
||||
else name = "ILLEGAL";
|
||||
10'b0101111_010: if (funct7[6:2] == 5'b00000) name = "FADD";
|
||||
else if (funct7[6:2] == 5'b00001) name = "FSUB";
|
||||
else if (funct7[6:2] == 5'b00010) name = "FMUL";
|
||||
else if (funct7[6:2] == 5'b00011) name = "FDIV";
|
||||
else if (funct7[6:2] == 5'b01011) name = "FSQRT";
|
||||
else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
|
||||
else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
|
||||
else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
|
||||
else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
|
||||
else if (funct7[6:2] == 5'b00100) name = "FSGNJX";
|
||||
else if (funct7[6:2] == 5'b10100) name = "FEQ";
|
||||
else name = "ILLEGAL";
|
||||
10'b1010011_???: if (funct7[6:2] == 5'b00000) name = "FADD";
|
||||
else if (funct7[6:2] == 5'b00001) name = "FSUB";
|
||||
else if (funct7[6:2] == 5'b00010) name = "FMUL";
|
||||
else if (funct7[6:2] == 5'b00011) name = "FDIV";
|
||||
else if (funct7[6:2] == 5'b01011) name = "FSQRT";
|
||||
else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
|
||||
else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
|
||||
else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
|
||||
else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
|
||||
else name = "ILLEGAL";
|
||||
10'b0000111_010: name = "FLW";
|
||||
10'b0100111_010: name = "FSW";
|
||||
10'b0000111_010: name = "FLD";
|
||||
10'b0100111_010: name = "FSD";
|
||||
default: name = "ILLEGAL";
|
||||
endcase
|
||||
endmodule
|
||||
|
||||
Loading…
Reference in New Issue
Block a user