David Harris
cb624fe679
Lint cleaning, riscv-arch-test testing
2021-09-09 11:05:12 -04:00
David Harris
a31828e925
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-08 16:00:12 -04:00
David Harris
30e2ec3987
Added testbench-arch for riscv-arch-test suite
2021-09-08 15:59:40 -04:00
Ross Thompson
6606eea27e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-09-08 12:47:03 -05:00
Ross Thompson
5bc90ef32f
Slight modification to wave file.
2021-09-08 10:40:46 -05:00
bbracker
5e9a39e755
fixed bug where M mode was sensitive to S mode traps
2021-09-07 19:14:39 -04:00
bbracker
28fed18421
No longer forcing CSRReadValM because that can feedback to corrupt some CSRs
2021-09-06 22:59:54 -04:00
Ross Thompson
00f50184d8
Changed name of memory in icache.
2021-09-06 20:54:52 -05:00
bbracker
58d478eb23
restore functionality of being able to turn on waves at a certain instruction count; restore linux-waves.do because wave.do seems to be in disrepair
2021-09-04 19:45:04 -04:00
Ross Thompson
5c2deab4e4
Partial multiway set associative icache.
2021-08-30 10:49:24 -05:00
Ross Thompson
4b0344898b
Fixed bugs I introduced to the icache.
2021-08-27 15:00:40 -05:00
Ross Thompson
de9e234ffa
Modified icache to no longer need StallF in the PCMux logic. Instead this is handled in the icachefsm.
...
One downside is it increases the icache complexity. However it also fixes an untested bug. If a region
was uncacheable it would have been possible for the request to be made multiple times. Now that is
not possible. Additionally spills were oscillating between the spill hit states without this change.
The impact was 'benign' as the final spilled instruction always had the correct upper 16 bits.
2021-08-27 11:03:36 -05:00
Ross Thompson
cbb47956cb
Swapped out the icachemem for cacheway. cacheway is modified to optionally support dirty bits.
2021-08-26 15:43:02 -05:00
Ross Thompson
642efbb563
Converted the icache type from logic to state type.
2021-08-26 10:41:42 -05:00
Ross Thompson
d2b3b7345e
Moved dcache fsm to separate module.
2021-08-25 21:37:10 -05:00
Ross Thompson
7be0a73db1
Moved LRU and storage for the LRU into a single module. Also found a subtle bug with the update address used to write the cache's memory.
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This was correct for the LRU but incorrect for the data, tag, valid, and dirty storage.
2021-08-25 21:09:42 -05:00
Ross Thompson
c48556836b
Removed generate around the dcache memories.
2021-08-25 13:27:26 -05:00
Ross Thompson
699053bab0
Updated linux test bench documenation and scripts.
2021-08-25 10:54:47 -05:00
Ross Thompson
b7972eafeb
Added function tracking to linux test bench.
2021-08-24 11:08:46 -05:00
Ross Thompson
c0667f30bb
Fixed bug with coremark do file. When I moved the testbench to have a common set of files i forgot to remove the old path reference to function_radix.sv in wally-coremark_bare.do.
2021-08-19 10:33:11 -05:00
Ross Thompson
4eca94268c
Added logic to linux test bench to not stop simulation on csr write faults.
2021-08-15 11:13:32 -05:00
Ross Thompson
15085448d7
Updated linux-wave.do to have cursors at the timer interrupt problem.
2021-08-13 17:29:37 -05:00
Ross Thompson
4f3f26c5cb
Switched ExceptionM to dcache to be just exceptions.
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Added test bench logic to hold forces until the W stage is unstalled.
2021-08-13 15:53:50 -05:00
Ross Thompson
a1c26a16d6
Cleaned up the linux testbench by removing old code and signals.
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Added back in the csr checking logic.
Added code to force timer, external, and software interrupts by using the expected
values from qemu's (m/s)cause registers.
Still need to prevent wally's timer interrupt.
2021-08-13 14:39:05 -05:00
Ross Thompson
467e24c05c
Fixed another bug with the atomic instrucitons implemention in the dcache.
2021-08-08 22:50:31 -05:00
Ross Thompson
20a04d8cee
Fixed another bug with AMO. If the CPU stalled as an AMO was finishing, the write to the
...
cache's SRAM would occur. Then in the next cycle the SRAM would be reread while stalled
providing the new update dated rather than the correct older value.
2021-08-08 11:42:10 -05:00
Ross Thompson
25533bdc49
Fixed the AMO dcache bug. The subword write needs to occur before the AMO logic.
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Fixed logic for trace update in the M and W stages. The M stage should not update if there
is an instruction fault.
2021-08-08 00:28:18 -05:00
Ross Thompson
839822d3b1
Now past the CLINT issues.
2021-08-06 16:16:39 -05:00
Ross Thompson
e1319a2fbe
Partial conversion of the linux trace checking to read in the file in the Memory Stage so it is possible to overwrite registers, memory, and interrupts.
2021-08-06 16:06:50 -05:00
Ross Thompson
d430659983
fixed the read timer issue but we still have problems with interrupts and i/o devices.
2021-08-06 10:16:06 -05:00
Ross Thompson
cd8a66353c
Patched up changes for wally-pipelined.do and wally-buildroot.do to support moved common testbench files.
2021-07-30 14:24:50 -05:00
Ross Thompson
ef66cdeecf
Moved the test bench modules to a common directory.
2021-07-30 14:16:14 -05:00
Ross Thompson
32ec457e09
Removed the hardware page table walker fault state from the icache so that the icache will only unstall CPU for 1 cycle.
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In the dcache we added a register to save the load read data in the event an itlb miss occurs concurrently with
the load in the memory stage. Under this situation we need to record the load ReadDataM into a temporary register,
SavedReadDataM. At this time the CPU is stall; however the walker is going to change the address in the dcache
which destroys this data. When leaving the PTW_READY state via a walker instruction fault or ITLB write we select
this SavedReadDataM so that the CPU can capture it.
2021-07-22 19:42:19 -05:00
Ross Thompson
007812dbdc
Moved the ReadDataW register into the datapath.
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The StallW from the hazard unit controls this.
Previously it was in the dcache and controlled by both the HPTW and hazard unit.
This caused an issue when the CPU expected the data to stay constant while
stalled, but the HPTW was causing the data to be modified.
2021-07-22 14:52:03 -05:00
Ross Thompson
89e22bc5e8
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-22 10:38:24 -05:00
Ross Thompson
e907d57340
Tested all numbers of ways for dcache 1, 2, 4, and 8.
2021-07-22 10:38:07 -05:00
bbracker
9dcd5d3622
fix UART RX FIFO bug where tail pointer can overtake head pointer
2021-07-22 02:09:41 -04:00
bbracker
cdcf419147
make address translator signals visible in waveview
2021-07-21 20:07:49 -04:00
Ross Thompson
511c36fb1b
Improved address bus names and usages in the walker, dcache, and tlbs.
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Merge branch 'walkerEnhance' into main
2021-07-21 14:55:09 -05:00
Ross Thompson
39fc9278ba
Fixed remaining bugs in 2 way set associative dcache.
2021-07-21 10:35:23 -05:00
Ross Thompson
8d0a552b5b
Partially working 2 way set associative d cache.
2021-07-20 17:51:42 -05:00
bbracker
bb2e3b1e02
remove busybear from regression because it is not keeping up with buildroot's changes to testbench-linux
2021-07-19 16:22:05 -04:00
bbracker
77b690faf0
make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset
2021-07-19 15:13:03 -04:00
Ross Thompson
5754b5f25f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-19 12:32:35 -05:00
Ross Thompson
2ee97efb9c
Fixed a complex bug in the dcache, where back to back loads would lose data on the load before a stall occurred. The solution was to modify the logic for SelAdrM in the dcache so that a stall would cause the SRAM to reread the address in the Memory stage rather than Execution stage. This also required updating the ReadDataWEn control so it is always enabled on ~StallW.
2021-07-19 12:32:16 -05:00
bbracker
2702064dda
change buildroot expectations to match reality
2021-07-19 13:20:53 -04:00
Ross Thompson
6ccbdc372d
Broken.
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Possible change to walker, dcache, tlb addressing.
Improves the naming of address signals.
But has a problem when the walker finishes the dcache does not get the correct
address on the cycle the DTLB is updated. This leads to incorrect index
selection in the dcache.
2021-07-19 10:33:27 -05:00
bbracker
64a81941ff
change memread testvectors to not left-shift bytes and half-words
2021-07-18 21:49:53 -04:00
bbracker
f4f3ef0307
linux testbench progress
2021-07-18 18:47:40 -04:00
Katherine Parry
3527620c0b
fdivsqrt inegrated, but not completley working
2021-07-18 14:03:37 -04:00
