Rose Thompson
8fb1673ab3
Updated email address authorship for my files.
2024-10-15 10:27:53 -05:00
Rose Thompson
f603d21826
Updated my name in multiple locations.
2024-08-21 10:50:39 -07:00
David Harris
af4403342f
renamed run_vcs.py to run_vcs, added instr/data in ebu
2024-07-03 08:02:38 -07:00
Ross Thompson
ab1ee3d69b
Removed *** from IFU, lrcs.
2024-06-19 09:40:35 -07:00
David Harris
301ded05f8
Unused signal cleanup
2024-06-18 08:15:48 -07:00
David Harris
8f09240e6c
Simplified outdated documentation pointers
2024-06-14 03:42:15 -07:00
David Harris
b1c9450b4a
Code cleanup: RAM, fdivsqrt
2024-06-14 03:35:05 -07:00
David Harris
6789f32154
Starting code cleanup
2024-06-14 02:54:43 -07:00
David Harris
3f195884e9
Defined bit sizes more precisely to help VCS lint and conform to coding style
2024-04-21 08:40:11 -07:00
Rose Thompson
4eb522123f
Changed D suffix to Delay in ebufsmarb.
2024-03-28 16:24:45 -05:00
Kunlin Han
22b59138f0
Remove all #delay from non-testbench.
2024-03-16 11:20:32 -07:00
Kunlin Han
8c67a76912
Remove all #delay from non-testbench.
2024-03-13 10:31:40 -07:00
David Harris
b386331cc8
Changed '0 to 0 where possible per Chapter 4 style guidelines
2024-03-06 05:48:17 -08:00
David Harris
66c1c71a56
Coverage improvements
2024-02-04 18:56:40 -08:00
David Harris
5d8d82414b
Coverage improvements
2024-02-04 11:40:38 -08:00
Rose Thompson
87d91c5b14
Coverage updates.
2024-02-01 12:12:01 -06:00
Rose Thompson
ccf61853cf
New coverage for ebu.
2024-01-31 14:55:25 -06:00
David Harris
f37c7bb1f6
Incorporated RAM_LATENCY and BURST_EN as parameters rather than define in code. Still need to update testbench to use this
2024-01-30 06:27:18 -08:00
David Harris
45e2317636
Added Wally github address to header comments
2024-01-29 05:38:11 -08:00
Rose Thompson
ff5554ca61
Atomics work correctly without a d cache.
2024-01-16 10:43:20 -06:00
Rose Thompson
dfe5ef4427
Added logic for the non-cache atomics.
2024-01-15 17:47:17 -06:00
Rose Thompson
82a786f185
Hmm. Verilator is complaining about the parameter width. I'm not sure why so I changed to 1 bit.
2024-01-15 17:36:01 -06:00
Rose Thompson
614a83331f
Fixed part of issue #405 .
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The non-cache version of the bus controller did not have the correct supression of BusCommitted for a read only controller.
2024-01-15 17:29:00 -06:00
Rose Thompson
588e1caeba
Found bugs in the no I$ implementation's abhinterface width. We were only testing XLEN=32. XLEN=64 did not properly align instructions not aligned to 8 byte boundaries.
2024-01-06 22:29:16 -06:00
Rose Thompson
8030b7d100
Added partial code for uncached amo operations.
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Minor fix for Makefile so coverage tests build.
2023-12-29 15:07:20 -06:00
Rose Thompson
d1456b2471
Progress on fixing cbo.zero for uncached memory regions.
2023-12-29 11:03:38 -06:00
Rose Thompson
195def5808
Extended the abhcacheinterface to zero a cacheline's worth of uncached memory on cbo.zero.
2023-11-27 21:24:30 -06:00
David Harris
d3ce683e06
Removed other unused signals from Verilog
2023-11-20 23:37:56 -08:00
Rose Thompson
0a4ed5515b
Merge branch 'main' into Zicclsm
2023-11-02 12:55:51 -05:00
Rose Thompson
f13b67b869
Preemptively fixed the bytemask bug before testing.
2023-10-30 15:47:46 -05:00
David Harris
3bb7539429
Fixed warnings of signed conversion and for Design Compiler
2023-10-24 14:01:43 -07:00
Ross Thompson
f895898d22
Improved the critical path even more. The Arty A7 works upto 19Mhz easily. Testing out 22Mhz now.
2023-07-21 16:31:26 -05:00
Harshini Srinath
9dc72c9e54
Update controllerinput.sv
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Program clean up
2023-06-10 18:26:06 -07:00
Harshini Srinath
dbdb3c69d3
Update ahbinterface.sv
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Program clean up
2023-06-10 18:18:16 -07:00
Harshini Srinath
dc0b95c4ac
Program clean up
2023-06-10 18:13:40 -07:00
Harshini Srinath
aafa5d6ec3
Update ebu.sv
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Code clean up
2023-06-09 08:53:27 -07:00
Ross Thompson
1299319d0b
More parameterization. Based on Lim's work. EBU, IFU (except bpred), and IEU done.
2023-05-24 14:56:02 -05:00
Ross Thompson
052bc95966
More parameterization. Copied Lim. Still no slow down.
2023-05-24 14:49:22 -05:00
Limnanthes Serafini
53847269da
More changes
2023-04-13 21:02:15 -07:00
Ross Thompson
366a96a0fc
Possible fix for issue 148.
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I found the problem. We use a Committed(F/M) signal to indicate the IFU or LSU has an ongoing cache or bus transaction and should not be interrupted. At the time of the mret, the IFU is fetching uncacheable invalid instructions asserting CommittedF. As the IFU finishes the request it unstalls the pipeline but continues to assert CommittedF. (This is not necessary for the IFU). In the same cycle the LSU d cache misses. Because CommittedF is blocking the interrupt the d cache submits a cache line fetch to the EBU.
I am thinking out loud here. At it's core the Committed(F/M) ensure memory operations are atomic and caches don't get into inconsistent states. Once the memory operation is completed the LSU/IFU removes the stall but continues to hold Committed(F/M) because the memory operation has completed and it would be wrong to allow an interrupt to occur with a completed load/store. However this is not true of the IFU. If we lower CommittedF once the operation is complete then this problem is solved. The interrupt won't be masked and the LSU will flush the d cache miss.
This requires a minor change in the cachebusfsm and cachefsm. I will report back after I've confirmed this works.
2023-03-28 14:47:08 -05:00
Ross Thompson
af8f1fd036
Renamed controllerinputstage to controllerinput to match book.
2023-03-24 17:57:02 -05:00
Ross Thompson
b5a58502d0
Replaced tabs -> spaces cache.
2023-03-24 15:15:38 -05:00
Ross Thompson
b518177a45
Updated EBU to replace tabs with spaces.
2023-03-24 15:01:38 -05:00
Ross Thompson
47f8e847f0
Renamed ebu signal.
2023-03-24 10:51:04 -05:00
David Harris
f1e87c5e69
Start of EBU coverage tests
2023-03-24 08:12:02 -07:00
Ross Thompson
fdfb80a818
Renamed ebuarbfsm to ebufsmarb to match figures.
2023-03-06 17:47:55 -06:00
David Harris
7cf98811f3
Parenthesized reduction operators to avoid DC lint
2023-02-04 18:49:47 -08:00
David Harris
78eb90715c
Removed pipelined level of hierarchy
2023-02-02 14:14:11 -08:00
