Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity
10,192 Commits 5 Branches 2 Tags 53 MiB
553bc0a72d
Commit Graph

1603 Commits

Author SHA1 Message Date
naichewa
3b7661dfd5 SckDiv Zero bug fixes 2024-09-03 14:58:46 -07:00
Rose Thompson
418bc6b23c Merge branch 'main' of github.com:openhwgroup/cvw 2024-08-21 16:24:10 -07:00
Rose Thompson
faffecf891 Merge branch 'main' of github.com:openhwgroup/cvw 2024-08-21 11:02:17 -07:00
Rose Thompson
01b623b8c4 Merge branch 'main' of github.com:openhwgroup/cvw 2024-08-21 11:02:08 -07:00
Rose Thompson
f603d21826 Updated my name in multiple locations. 2024-08-21 10:50:39 -07:00
Jacob Pease
938879c5a4 Update PREADY signal to not stall during transmission on reads to read only registers. 2024-08-21 12:39:01 -05:00
Jacob Pease
b7edffdfd4 Removed now inaccurate comments. 2024-08-20 16:38:15 -05:00
Jacob Pease
f960662e93 Removed now inaccurate comments. 2024-08-20 16:38:15 -05:00
Jacob Pease
d8b75440b6 With Naiche's help, we fixed the SPI controllers clock polarity and phase settings. Added conditions to the SPI regression tests. 2024-08-20 16:24:37 -05:00
Jacob Pease
baad4e0fd2 With Naiche's help, we fixed the SPI controllers clock polarity and phase settings. Added conditions to the SPI regression tests. 2024-08-20 16:24:37 -05:00
Jacob Pease
43b17b5058 Update SPI peripheral to accept writes to FIFO always. Worked on this together with Naiche and Rose. 2024-08-20 14:40:50 -05:00
Jacob Pease
9ac889e3e8 Update SPI peripheral to accept writes to FIFO always. Worked on this together with Naiche and Rose. 2024-08-20 14:40:50 -05:00
David Harris
8e62c578ea Detect illegal writes to URO HPM counters 2024-08-15 10:43:20 -07:00
David Harris
e5d262063f Detect illegal writes to URO HPM counters 2024-08-15 10:43:20 -07:00
David Harris
f0f0e96eee Fixes mstatus.FS to also be set when a FP operation sets a floating-point flag even if it doesnt write a FP register 2024-08-13 07:34:58 -07:00
David Harris
125884eb74 Fixes mstatus.FS to also be set when a FP operation sets a floating-point flag even if it doesnt write a FP register 2024-08-13 07:34:58 -07:00
David Harris
ca82a63de6 Fixed c.slli hint discovered by Lee (Issue 910) 2024-08-13 06:45:45 -07:00
David Harris
705ee60618 Fixed c.slli hint discovered by Lee (Issue 910) 2024-08-13 06:45:45 -07:00
David Harris
64709bccab Fixed fldsp decompress with rd = 0 2024-08-08 21:45:57 -07:00
David Harris
b334dc50a4 Fixed fldsp decompress with rd = 0 2024-08-08 21:45:57 -07:00
David Harris
010038ec32 Depricate conditional generation based on A_SUPPORTED, which is now computed from ZALRSC_SUPPORTED and ZAAMO_SUPPORTED 2024-08-08 05:27:35 -07:00
David Harris
fa98ae8c30 Depricate conditional generation based on A_SUPPORTED, which is now computed from ZALRSC_SUPPORTED and ZAAMO_SUPPORTED 2024-08-08 05:27:35 -07:00
Rose Thompson
7164841f83 Added padding into the hw rvvi format. 2024-08-06 18:34:46 -05:00
Jacob Pease
f8f16d2d34 Added and extra header and changed the comments to be accurate in ram1p1rwbe.sv 2024-08-06 17:36:42 -05:00
Jacob Pease
2dc7e0f76f Added and extra header and changed the comments to be accurate in ram1p1rwbe.sv 2024-08-06 17:36:42 -05:00
Jacob Pease
11ca2567b8 Merge branch 'main' of github.com:openhwgroup/cvw into spiboot 2024-08-06 17:09:39 -05:00
Jacob Pease
af2344d2d5 Merge branch 'main' of github.com:openhwgroup/cvw into spiboot 2024-08-06 17:09:39 -05:00
Jacob Pease
bd07a60c07 Updated wally source files for zsbl testing. 2024-08-02 15:33:57 -05:00
Jacob Pease
11a057b0b3 Updated wally source files for zsbl testing. 2024-08-02 15:33:57 -05:00
Jacob Pease
2ed0b239e8 Added preload pointing to data.mem in ram1p1rwbe.sv 2024-08-02 15:21:15 -05:00
Jacob Pease
1e20d5aea6 Added preload pointing to data.mem in ram1p1rwbe.sv 2024-08-02 15:21:15 -05:00
Rose Thompson
6496454054
Merge pull request #895 from davidharrishmc/dev 
Fix Issue 894 about floating-point decoding of reserved rm/frm
 2024-07-25 11:51:32 -05:00
Rose Thompson
2e4ca4c876 Merge pull request #895 from davidharrishmc/dev 
Fix Issue 894 about floating-point decoding of reserved rm/frm
 2024-07-25 11:51:32 -05:00
David Harris
faa1378920 Legalized PMPconfig WARL 2024-07-25 09:43:54 -07:00
David Harris
7360be1234 Legalized PMPconfig WARL 2024-07-25 09:43:54 -07:00
David Harris
d5af25ffbf CHeck legal rnum field when decoding aes64ks1i 2024-07-25 09:19:23 -07:00
David Harris
c637e40058 CHeck legal rnum field when decoding aes64ks1i 2024-07-25 09:19:23 -07:00
Jacob Pease
6fc10adc25 Added ability to split boot.memfile into boot.mem and data.mem. 2024-07-25 11:19:15 -05:00
Jacob Pease
336a413f31 Added ability to split boot.memfile into boot.mem and data.mem. 2024-07-25 11:19:15 -05:00
David Harris
5bf7250687 Issue #894: trap on floating-point ops with reserved rounding modes: detect Zfa flt 2024-07-25 09:09:13 -07:00
David Harris
7234abebef Issue #894: trap on floating-point ops with reserved rounding modes: detect Zfa flt 2024-07-25 09:09:13 -07:00
David Harris
f7dd49cc6c Issue #894: trap on floating-point ops with reserved rounding modes 2024-07-25 06:59:58 -07:00
David Harris
337e40ac1b Issue #894: trap on floating-point ops with reserved rounding modes 2024-07-25 06:59:58 -07:00
Rose Thompson
b1a711ae0f Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim. 2024-07-24 12:47:50 -05:00
Rose Thompson
c11036358a Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim. 2024-07-24 12:47:50 -05:00
Rose Thompson
9404a339ee Handled all remaining verilator warnings in the rvvi synth code. Now it's time to take on the verilog-ethernet warnings. 2024-07-23 17:44:37 -05:00
Rose Thompson
7960f26e84 Handled all remaining verilator warnings in the rvvi synth code. Now it's time to take on the verilog-ethernet warnings. 2024-07-23 17:44:37 -05:00
Rose Thompson
6c212ebf0e Changes are confirmed to work on the FPGA. 2024-07-23 17:39:38 -05:00
Rose Thompson
35efbd6a54 Changes are confirmed to work on the FPGA. 2024-07-23 17:39:38 -05:00
Jacob Pease
c18b3d814d Fixed verilog bugs. 2024-07-23 17:26:39 -05:00
Jacob Pease
f1cc7dd5a3 Fixed verilog bugs. 2024-07-23 17:26:39 -05:00
Rose Thompson
e8e71ad643 Code cleanup. 2024-07-23 16:35:05 -05:00
Rose Thompson
bfb3b63a24 Code cleanup. 2024-07-23 16:35:05 -05:00
Rose Thompson
57ea39d685 Fixed rvvi csr counting. 2024-07-23 16:22:23 -05:00
Rose Thompson
fe9ac36928 Fixed rvvi csr counting. 2024-07-23 16:22:23 -05:00
Rose Thompson
54e0289608 Fixed bugs in the rvvi synth logic which encoded csr instructions. 2024-07-23 16:16:11 -05:00
Rose Thompson
da2511c63c Fixed bugs in the rvvi synth logic which encoded csr instructions. 2024-07-23 16:16:11 -05:00
Rose Thompson
1eff86b7ae Down to 3 verilator warnings in rvvisynth and a 40 warnings in verilog-ethernet. 2024-07-23 13:18:03 -05:00
Rose Thompson
7bc04702a7 Down to 3 verilator warnings in rvvisynth and a 40 warnings in verilog-ethernet. 2024-07-23 13:18:03 -05:00
Rose Thompson
c463201d68 Moved all rvvi files to rvvi directory. 2024-07-23 13:03:21 -05:00
Rose Thompson
f20b82b14e Moved all rvvi files to rvvi directory. 2024-07-23 13:03:21 -05:00
Rose Thompson
825dbefcb2 Fixed bus width error. Have to check this FPGA to make sure this didn't break anything. 2024-07-23 12:26:03 -05:00
Rose Thompson
d706b5b898 Fixed bus width error. Have to check this FPGA to make sure this didn't break anything. 2024-07-23 12:26:03 -05:00
Rose Thompson
bb74a0f96b Resolved more lint errors in the rvvi synthesized hardware. 2024-07-23 12:23:04 -05:00
Rose Thompson
b30656447f Resolved more lint errors in the rvvi synthesized hardware. 2024-07-23 12:23:04 -05:00
Rose Thompson
94a1ce32e7 Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-07-22 17:48:34 -05:00
Rose Thompson
c6c2240630 Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-07-22 17:48:34 -05:00
Rose Thompson
121342f4cc Updated the verilog-ethernet repo to remove most of the warnings. Updated the fpga constraints so the ILA is more useful when using RVVI. 2024-07-22 16:12:06 -05:00
Rose Thompson
3c06556833 Updated the verilog-ethernet repo to remove most of the warnings. Updated the fpga constraints so the ILA is more useful when using RVVI. 2024-07-22 16:12:06 -05:00
Jacob Pease
c50df29e58 Merge branch 'main' of github.com:openhwgroup/cvw into spiboot 2024-07-22 13:06:05 -05:00
Jacob Pease
6a9141e3be Merge branch 'main' of github.com:openhwgroup/cvw into spiboot 2024-07-22 13:06:05 -05:00
Jacob Pease
a722c3c0a1 Removed the old SDC. Added a second SPI peripheral that now will be used to control the SD card. SPI peripheral now outputs SPICLK. Removed references to the now non-existent external SDC in uncore. Removed all of the AXI Xilinx IP. 2024-07-22 12:36:39 -05:00
Jacob Pease
a506d76149 Removed the old SDC. Added a second SPI peripheral that now will be used to control the SD card. SPI peripheral now outputs SPICLK. Removed references to the now non-existent external SDC in uncore. Removed all of the AXI Xilinx IP. 2024-07-22 12:36:39 -05:00
Rose Thompson
00c30239bf Cleaned up rvvisynth.sv 2024-07-22 12:22:41 -05:00
Rose Thompson
35e69944fa Cleaned up rvvisynth.sv 2024-07-22 12:22:41 -05:00
Rose Thompson
7223b15134 Merge branch 'rvvi' 2024-07-22 12:01:01 -05:00
Rose Thompson
02f108345a Merge branch 'rvvi' 2024-07-22 12:01:01 -05:00
David Harris
c4400dfeb0 Fixed WARL bug on MTVEC/STVEC alignment to 64 in vectored mode 2024-07-22 08:45:08 -07:00
David Harris
13f1aa1ebf Fixed WARL bug on MTVEC/STVEC alignment to 64 in vectored mode 2024-07-22 08:45:08 -07:00
Rose Thompson
9471dcd296 Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes. 
Adds three new configuration parameters to control enabling the RVVI packetizer and how much latency should exist between packets and the initial startup delay.
 2024-07-19 17:08:47 -05:00
Rose Thompson
0d40b8c933 Cleanup in prep to merge the rvvi branch into main. 2024-07-19 15:48:20 -05:00
Rose Thompson
a324e79b6f Updated the ethernet frame gap for a faster computer. 2024-07-19 13:12:13 -05:00
David Harris
c64c12dc6c Detect illegal compressed immediates, hints 2024-07-18 22:48:32 -07:00
David Harris
12c8449275 Detect illegal compressed immediates, hints 2024-07-18 22:48:32 -07:00
David Harris
945722cd5b Neatly formatted decompress.sv 2024-07-18 22:01:43 -07:00
David Harris
bd1658754f Neatly formatted decompress.sv 2024-07-18 22:01:43 -07:00
David Harris
ebea314a6e Modified decompressor to look for illegal x0 values and hints 2024-07-18 21:38:17 -07:00
David Harris
a4e84d6f15 Modified decompressor to look for illegal x0 values and hints 2024-07-18 21:38:17 -07:00
David Harris
3b4726ea99 Check legal compressed nonzero destination registers, add c.nop decoding 2024-07-18 09:30:16 -07:00
David Harris
1637f4f1e3 Check legal compressed nonzero destination registers, add c.nop decoding 2024-07-18 09:30:16 -07:00
David Harris
df063acf61 Refactored decompression to use simpler default illegal instruction 2024-07-18 08:26:58 -07:00
David Harris
566583639d Refactored decompression to use simpler default illegal instruction 2024-07-18 08:26:58 -07:00
David Harris
25f271064f Fixed slli.uw bug reported by Lee Moore 16 July 2024 2024-07-16 09:28:05 -07:00
David Harris
8f83ff1a94 Fixed slli.uw bug reported by Lee Moore 16 July 2024 2024-07-16 09:28:05 -07:00
Ross Thompson
f0096f5a43 Yay. It's actually working! The FPGA/ImperasDV hybrid is working. 2024-07-10 15:10:37 -05:00
Ross Thompson
e6dc962d11 Yay! the trigger is correctly working now! 2024-07-10 12:05:10 -05:00
Ross Thompson
cf986b5fb8 Really close to having the trigger in module work. 
Can trigger on the data of the correct frame, but trigger in is still not
working.
 2024-07-09 19:04:51 -05:00
David Harris
84c687080d Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2024-07-05 21:42:26 -07:00
David Harris
9f5e7b8653
Merge pull request #851 from kevindkim723/intdivb 
Reduce Bit widths for IDIV on FPU
 2024-07-05 21:42:19 -07:00
David Harris
ffb248dc65 Fixed issue 868 about tlbmisc.S coverage test failing due to HPTW writing wrong address when updateing A bit 2024-07-05 21:32:57 -07:00