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Update PREADY signal to not stall during transmission on reads to read only registers.

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This commit is contained in:
Jacob Pease 2024-08-21 12:39:01 -05:00
parent b7edffdfd4
commit 938879c5a4
1 changed files with 1 additions and 1 deletions
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src/uncore/spi_apb.sv
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@ -148,7 +148,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
// APB access
assign Entry = {PADDR[7:2],2'b00}; // 32-bit word-aligned accesses
assign Memwrite = PWRITE & PENABLE & PSEL; // Only write in access phase
assign PREADY = Entry == SPI_TXDATA | Entry == SPI_RXDATA | TransmitInactive; // Tie PREADY to transmission for hardware interlock
assign PREADY = Entry == SPI_TXDATA | Entry == SPI_RXDATA | Entry == SPI_IP | TransmitInactive; // Tie PREADY to transmission for hardware interlock
// Account for subword read/write circuitry
// -- Note SPI registers are 32 bits no matter what; access them with LW SW.