mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of github.com:openhwgroup/cvw
This commit is contained in:
Rose Thompson
Rose
commit
01b623b8c4
300
.gitignore
vendored
300
.gitignore
vendored
@ -1,78 +1,46 @@
|
||||
# General file extensions to ignore
|
||||
.nfs*
|
||||
*.objdump*
|
||||
*.o
|
||||
*.d
|
||||
*.a
|
||||
*.vstf
|
||||
*.vcd
|
||||
*.signature.output
|
||||
*.dtb
|
||||
*.log
|
||||
*.map
|
||||
*.elf*
|
||||
*.list
|
||||
|
||||
# General directories to ignore
|
||||
.vscode/
|
||||
__pycache__/
|
||||
**/work*
|
||||
**/wally_*.log
|
||||
/**/obj_dir*
|
||||
/**/gmon*
|
||||
|
||||
.nfs*
|
||||
|
||||
__pycache__/
|
||||
.vscode/
|
||||
|
||||
#External repos
|
||||
addins/riscv-arch-test/Makefile.include
|
||||
addins/riscv-tests/target
|
||||
addins/TestFloat-3e/build/Linux-x86_64-GCC/*
|
||||
|
||||
|
||||
#vsim work files to ignore
|
||||
transcript
|
||||
vsim.wlf
|
||||
wlft*
|
||||
wlft*
|
||||
/imperas-riscv-tests/FunctionRadix_32.addr
|
||||
/imperas-riscv-tests/FunctionRadix_64.addr
|
||||
/imperas-riscv-tests/FunctionRadix.addr
|
||||
/imperas-riscv-tests/ProgramMap.txt
|
||||
/imperas-riscv-tests/logs
|
||||
*.o
|
||||
*.d
|
||||
*.vstf
|
||||
testsBP/*/*/*.elf*
|
||||
testsBP/*/OBJ/*
|
||||
testsBP/*/*.a
|
||||
tests/wally-riscv-arch-test/riscv-test-suite/*/I/*/*
|
||||
tests/riscof/riscof_work/
|
||||
# Tests
|
||||
tests/riscof/config32.ini
|
||||
tests/riscof/config32e.ini
|
||||
tests/riscof/config64.ini
|
||||
tests/linux-testgen/linux-testvectors/*
|
||||
!tests/linux-testgen/linux-testvectors/tvCopier.py
|
||||
!tests/linux-testgen/linux-testvectors/tvLinker.sh
|
||||
!tests/linux-testgen/linux-testvectors/tvUnlinker.sh
|
||||
tests/linux-testgen/buildroot
|
||||
tests/linux-testgen/buildroot-image-output
|
||||
tests/linux-testgen/buildroot-config-src/main.config.old
|
||||
tests/linux-testgen/buildroot-config-src/linux.config.old
|
||||
tests/linux-testgen/buildroot-config-src/busybox.config.old
|
||||
tests/riscof/riscof_work/
|
||||
tests/wally-riscv-arch-test/riscv-test-suite/*/I/*/**
|
||||
tests/fp/vectors/*.tv
|
||||
tests/fp/combined_IF_vectors/IF_vectors/*.tv
|
||||
tests/custom/*/*/
|
||||
tests/custom/*/*/*.memfile
|
||||
tests/riscvdv
|
||||
tests/functcov
|
||||
|
||||
# Linux
|
||||
linux/buildroot
|
||||
linux/testvector-generation/boottrace.S
|
||||
linux/testvector-generation/boottrace_disasm.log
|
||||
sim/slack-notifier/slack-webhook-url.txt
|
||||
fpga/generator/IP
|
||||
fpga/generator/vivado.*
|
||||
fpga/generator/.Xil/*
|
||||
fpga/generator/WallyFPGA*
|
||||
fpga/generator/reports/
|
||||
fpga/generator/*.log
|
||||
fpga/generator/*.jou
|
||||
*.objdump*
|
||||
*.signature.output
|
||||
examples/asm/sumtest/sumtest
|
||||
examples/asm/example/example
|
||||
examples/C/sum/sum
|
||||
examples/C/fir/fir
|
||||
examples/fp/softfloat_demo/softfloat_demo
|
||||
examples/fp/softfloat_demo/softfloat_demoDP
|
||||
examples/fp/softfloat_demo/softfloat_demoQP
|
||||
examples/fp/softfloat_demo/softfloat_demoSP
|
||||
examples/fp/fpcalc/fpcalc
|
||||
examples/fp/sqrttest/sqrttest
|
||||
examples/C/inline/inline
|
||||
examples/C/mcmodel/mcmodel
|
||||
examples/C/sum_mixed/sum_mixed
|
||||
examples/asm/trap/trap
|
||||
examples/asm/etc/pause
|
||||
src/fma/fma16_testgen
|
||||
linux/devicetree/debug/*
|
||||
!linux/devicetree/debug/dump-dts.sh
|
||||
linux/testvector-generation/genCheckpoint.gdb
|
||||
@ -80,10 +48,30 @@ linux/testvector-generation/silencePipe
|
||||
linux/testvector-generation/silencePipe.control
|
||||
linux/testvector-generation/fixBinMem
|
||||
linux/testvector-generation/qemu-serial
|
||||
*.dtb
|
||||
|
||||
# FPGA
|
||||
fpga/generator/IP
|
||||
fpga/generator/vivado.*
|
||||
fpga/generator/.Xil/*
|
||||
fpga/generator/WallyFPGA*
|
||||
fpga/generator/reports/
|
||||
fpga/generator/*.jou
|
||||
fpga/src/sdc/*
|
||||
fpga/src/sdc.tar.gz
|
||||
fpga/src/CopiedFiles_do_not_add_to_repo/*
|
||||
fpga/generator/sim/imp-funcsim.v
|
||||
fpga/generator/sim/imp-timesim.sdf
|
||||
fpga/generator/sim/imp-timesim.v
|
||||
fpga/generator/sim/syn-funcsim.v
|
||||
fpga/rvvidaemon/rvvidaemon
|
||||
fpga/zsbl/OBJ/*
|
||||
fpga/zsbl/bin/*
|
||||
fpga/src/boot.mem
|
||||
fpga/src/data.mem
|
||||
|
||||
# Synthesis
|
||||
synthDC/WORK
|
||||
synthDC/alib-52
|
||||
synthDC/*.log
|
||||
synthDC/*.svf
|
||||
synthDC/runs/
|
||||
synthDC/newRuns
|
||||
@ -92,128 +80,51 @@ synthDC/ppa/plots
|
||||
synthDC/wallyplots/
|
||||
synthDC/runArchive
|
||||
synthDC/hdl
|
||||
sim/power.saif
|
||||
tests/fp/vectors
|
||||
synthDC/Summary.csv
|
||||
tests/custom/work
|
||||
tests/custom/*/*/*.list
|
||||
tests/custom/*/*/*.elf
|
||||
tests/custom/*/*/*.map
|
||||
tests/custom/*/*/*.memfile
|
||||
tests/custom/crt0/*.a
|
||||
tests/custom/*/*.elf*
|
||||
sim/sd_model.log
|
||||
fpga/src/sdc/*
|
||||
fpga/src/sdc.tar.gz
|
||||
fpga/src/CopiedFiles_do_not_add_to_repo/*
|
||||
fpga/src/boot.mem
|
||||
fpga/src/data.mem
|
||||
sim/branch.log
|
||||
/fpga/generator/sim/imp-funcsim.v
|
||||
/fpga/generator/sim/imp-timesim.sdf
|
||||
/fpga/generator/sim/imp-timesim.v
|
||||
/fpga/generator/sim/syn-funcsim.v
|
||||
external
|
||||
sim/results
|
||||
tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/src/*.S
|
||||
tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/Makefrag
|
||||
sim/branch_BP_GSHARE10.log
|
||||
sim/branch_BP_GSHARE16.log
|
||||
sim/questa/imperas.log
|
||||
sim/results-error/
|
||||
sim/test1.rep
|
||||
sim/questa/vsim.log
|
||||
tests/coverage/*.elf
|
||||
*.elf.memfile
|
||||
sim/*Cache.log
|
||||
sim/branch
|
||||
tests/fp/combined_IF_vectors/IF_vectors/*.tv
|
||||
/sim/branch-march14.tar.gz
|
||||
/sim/gshareforward-no-class
|
||||
/sim/lint-wally_32
|
||||
/sim/lint-wally_32e
|
||||
/sim/local16.txt
|
||||
/sim/localhistory_m6k10_results_april24.txt
|
||||
/sim/log.log
|
||||
/sim/obj_dir/Vtestbench.cpp
|
||||
/sim/obj_dir/Vtestbench.h
|
||||
/sim/obj_dir/Vtestbench.mk
|
||||
/sim/obj_dir/Vtestbench__ConstPool_0.cpp
|
||||
/sim/obj_dir/Vtestbench__Syms.cpp
|
||||
/sim/obj_dir/Vtestbench__Syms.h
|
||||
/sim/obj_dir/Vtestbench___024root.h
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__0.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__0__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__1.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__10.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__11.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__1__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__2.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__2__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__3.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__3__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__4.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__4__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__5.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__5__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__6.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__7.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__8.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__9.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hfc24d085__0.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hfc24d085__0__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench___024unit.h
|
||||
/sim/obj_dir/Vtestbench___024unit__DepSet_hf87c9ffd__0__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench___024unit__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench__verFiles.dat
|
||||
/sim/obj_dir/Vtestbench_classes.mk
|
||||
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9.h
|
||||
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h34d4af8f__0.cpp
|
||||
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h34d4af8f__0__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h845a114e__0.cpp
|
||||
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h845a114e__0__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h845a114e__1.cpp
|
||||
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench_tlbram__Pz1_T20.h
|
||||
/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__DepSet_h3df7cb71__0.cpp
|
||||
/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__DepSet_hab70f5b0__0.cpp
|
||||
/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__DepSet_hab70f5b0__0__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__Slow.cpp
|
||||
sim/bp-results/*.log
|
||||
sim/branch*.log
|
||||
/tests/custom/fpga-test-sdc/bin/fpga-test-sdc
|
||||
|
||||
# Benchmarks
|
||||
benchmarks/embench/wally*.json
|
||||
benchmarks/embench/run*
|
||||
sim/cfi.log
|
||||
benchmarks/coremark/coremark_results.csv
|
||||
|
||||
# Simulation
|
||||
sim/*.svg
|
||||
sim/power.saif
|
||||
sim/results
|
||||
sim/results-error/
|
||||
sim/test1.rep
|
||||
sim/branch
|
||||
sim/branch-march14.tar.gz
|
||||
sim/gshareforward-no-class
|
||||
sim/local16.txt
|
||||
sim/localhistory_m6k10_results_april24.txt
|
||||
sim/cfi/*
|
||||
sim/branch/*
|
||||
sim/obj_dir
|
||||
examples/verilog/fulladder/obj_dir
|
||||
examples/verilog/fulladder/fulladder.vcd
|
||||
config/deriv
|
||||
docs/docker/buildroot-config-src
|
||||
docs/docker/testvector-generation
|
||||
sim/questa/cov
|
||||
sim/questa/fcovrvvi
|
||||
sim/questa/fcovrvvi_logs
|
||||
sim/questa/fcovrvvi_ucdb
|
||||
sim/covhtmlreport/
|
||||
|
||||
# Questa
|
||||
sim/questa/logs
|
||||
sim/questa/wkdir
|
||||
sim/questa/ucdb
|
||||
sim/questa/fcov
|
||||
sim/questa/cov
|
||||
sim/questa/fcov
|
||||
sim/questa/fcovrvvi
|
||||
sim/questa/fcovrvvi_logs
|
||||
sim/questa/fcovrvvi_ucdb
|
||||
sim/questa/fcov_logs
|
||||
sim/questa/fcov_ucdb
|
||||
sim/verilator/logs
|
||||
sim/verilator/wkdir
|
||||
sim/questa/functcov_logs
|
||||
sim/questa/functcov_ucdbs
|
||||
sim/questa/functcov
|
||||
sim/questa/riscv.ucdb
|
||||
transcript
|
||||
vsim.wlf
|
||||
wlft*
|
||||
|
||||
# VCS
|
||||
sim/vcs/logs
|
||||
sim/vcs/wkdir
|
||||
sim/vcs/ucdb
|
||||
benchmarks/coremark/coremark_results.csv
|
||||
fpga/zsbl/OBJ/*
|
||||
fpga/zsbl/bin/*
|
||||
sim/*.svg
|
||||
sim/vcs/csrc
|
||||
sim/vcs/profileReport*
|
||||
sim/vcs/program.out
|
||||
@ -222,17 +133,13 @@ sim/vcs/simprofile_dir
|
||||
sim/vcs/ucli.key
|
||||
sim/vcs/verdi_config_file
|
||||
sim/vcs/vcdplus.vpd
|
||||
sim/*/testbench.vcd
|
||||
sim/questa/imperas.log
|
||||
sim/questa/functcov.log
|
||||
sim/questa/functcov_logs/*
|
||||
sim/questa/functcov_ucdbs/*
|
||||
sim/questa/functcov
|
||||
sim/questa/riscv.ucdb
|
||||
sim/questa/riscv.ucdb.log
|
||||
sim/questa/riscv.ucdb.summary.log
|
||||
sim/questa/riscv.ucdb.testdetails.log
|
||||
tests/riscvdv
|
||||
sim/vcs/simprofile*
|
||||
|
||||
# Verilator
|
||||
sim/verilator/logs
|
||||
sim/verilator/wkdir
|
||||
|
||||
# Examples
|
||||
examples/verilog/fulladder/csrc/
|
||||
examples/verilog/fulladder/profileReport.html
|
||||
examples/verilog/fulladder/profileReport.json
|
||||
@ -242,10 +149,27 @@ examples/verilog/fulladder/simprofile_dir/
|
||||
examples/verilog/fulladder/simv.daidir/
|
||||
examples/verilog/fulladder/ucli.key
|
||||
examples/verilog/fulladder/verdi_config_file
|
||||
examples/fp/softfloat_demo/softfloat_demo
|
||||
examples/fp/softfloat_demo/softfloat_demoDP
|
||||
examples/fp/softfloat_demo/softfloat_demoQP
|
||||
examples/fp/softfloat_demo/softfloat_demoSP
|
||||
examples/fp/fpcalc/fpcalc
|
||||
examples/fp/sqrttest/sqrttest
|
||||
examples/crypto/gfmul/gfmul
|
||||
tests/functcov
|
||||
tests/functcov/*
|
||||
tests/functcov/*/*
|
||||
sim/vcs/simprofile*
|
||||
sim/verilator/verilator.log
|
||||
/fpga/rvvidaemon/rvvidaemon
|
||||
examples/C/fir/fir
|
||||
examples/C/inline/inline
|
||||
examples/C/mcmodel/mcmodel_medany
|
||||
examples/C/mcmodel/mcmodel_medlow
|
||||
examples/C/sum/sum
|
||||
examples/C/sum_mixed/sum_mixed
|
||||
examples/asm/sumtest/sumtest
|
||||
examples/asm/example/example
|
||||
examples/asm/trap/trap
|
||||
examples/asm/etc/pause
|
||||
|
||||
# Other
|
||||
external
|
||||
config/deriv
|
||||
sim/slack-notifier/slack-webhook-url.txt
|
||||
docs/docker/buildroot-config-src
|
||||
docs/docker/testvector-generation
|
||||
|
||||
39
Makefile
39
Makefile
@ -4,45 +4,36 @@
|
||||
|
||||
SIM = ${WALLY}/sim
|
||||
|
||||
all:
|
||||
make riscof
|
||||
make zsbl
|
||||
make testfloat
|
||||
# make verify
|
||||
make coverage
|
||||
# make benchmarks
|
||||
.PHONY: all riscof testfloat combined_IF_vectors zsbl benchmarks coremark embench coverage clean
|
||||
|
||||
all: riscof testfloat combined_IF_vectors zsbl coverage # benchmarks
|
||||
|
||||
# riscof builds the riscv-arch-test and wally-riscv-arch-test suites
|
||||
riscof:
|
||||
make -C sim
|
||||
$(MAKE) -C sim
|
||||
|
||||
testfloat:
|
||||
cd ${WALLY}/addins/SoftFloat-3e/build/Linux-x86_64-GCC; make
|
||||
cd ${WALLY}/addins/TestFloat-3e/build/Linux-x86_64-GCC; make
|
||||
cd ${WALLY}/tests/fp; ./create_all_vectors.sh
|
||||
$(MAKE) -C ${WALLY}/tests/fp vectors
|
||||
|
||||
combined_IF_vectors: testfloat riscof
|
||||
$(MAKE) -C ${WALLY}/tests/fp combined_IF_vectors
|
||||
|
||||
zsbl:
|
||||
$(MAKE) -C ${WALLY}/fpga/zsbl
|
||||
|
||||
verify:
|
||||
cd ${SIM}; ./regression-wally
|
||||
cd ${SIM}/sim; ./sim-testfloat-batch all
|
||||
make imperasdv
|
||||
|
||||
benchmarks:
|
||||
make coremark
|
||||
make embench
|
||||
$(MAKE) coremark
|
||||
$(MAKE) embench
|
||||
|
||||
coremark:
|
||||
cd ${WALLY}/benchmarks/coremark; make; make run
|
||||
cd ${WALLY}/benchmarks/coremark; $(MAKE); $(MAKE) run
|
||||
|
||||
embench:
|
||||
cd ${WALLY}/benchmarks/embench; make; make run
|
||||
cd ${WALLY}/benchmarks/embench; $(MAKE); $(MAKE) run
|
||||
|
||||
coverage:
|
||||
make -C tests/coverage
|
||||
|
||||
$(MAKE) -C tests/coverage
|
||||
|
||||
clean:
|
||||
make clean -C sim
|
||||
|
||||
$(MAKE) clean -C sim
|
||||
$(MAKE) clean -C ${WALLY}/tests/fp
|
||||
|
||||
Binary file not shown.
@ -1,43 +1,42 @@
|
||||
dst := IP
|
||||
|
||||
# vcu118
|
||||
# export XILINX_PART := xcvu9p-flga2104-2L-e
|
||||
# export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
|
||||
# export board := vcu118
|
||||
all: ArtyA7
|
||||
|
||||
# vcu108
|
||||
# export XILINX_PART := xcvu095-ffva2104-2-e
|
||||
# export XILINX_BOARD := xilinx.com:vcu108:part0:1.7
|
||||
# export board := vcu108
|
||||
.PHONY: ArtyA7 vcu118 vcu108
|
||||
|
||||
# Arty A7
|
||||
export XILINX_PART := xc7a100tcsg324-1
|
||||
export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
|
||||
export board := ArtyA7
|
||||
ArtyA7: export XILINX_PART := xc7a100tcsg324-1
|
||||
ArtyA7: export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
|
||||
ArtyA7: export board := ArtyA7
|
||||
ArtyA7: FPGA_Arty
|
||||
|
||||
# for Arty A7 and S7 boards
|
||||
all: FPGA_Arty
|
||||
vcu118: export XILINX_PART := xcvu9p-flga2104-2L-e
|
||||
vcu118: export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
|
||||
vcu118: export board := vcu118
|
||||
vcu118: FPGA_VCU
|
||||
|
||||
# VCU 108 and VCU 118 boards
|
||||
#all: FPGA_VCU
|
||||
vcu108: export XILINX_PART := xcvu095-ffva2104-2-e
|
||||
vcu108: export XILINX_BOARD := xilinx.com:vcu108:part0:1.7
|
||||
vcu108: export board := vcu108
|
||||
vcu108: FPGA_VCU
|
||||
|
||||
.PHONY: FPGA_Arty FPGA_VCU
|
||||
FPGA_Arty: PreProcessFiles IP_Arty
|
||||
vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
|
||||
|
||||
FPGA_VCU: PreProcessFiles IP_VCU
|
||||
vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
|
||||
|
||||
# Generate IP Blocks
|
||||
.PHONY: IP_Arty IP_VCU
|
||||
IP_VCU: $(dst)/xlnx_proc_sys_reset.log \
|
||||
$(dst)/xlnx_ddr4-$(board).log \
|
||||
MEM_VCU \
|
||||
$(dst)/xlnx_axi_clock_converter.log \
|
||||
$(dst)/xlnx_ahblite_axi_bridge.log \
|
||||
$(dst)/xlnx_axi_crossbar.log \
|
||||
$(dst)/xlnx_axi_dwidth_conv_32to64.log \
|
||||
$(dst)/xlnx_axi_dwidth_conv_64to32.log \
|
||||
$(dst)/xlnx_axi_prtcl_conv.log
|
||||
|
||||
IP_Arty: $(dst)/xlnx_proc_sys_reset.log \
|
||||
$(dst)/xlnx_ddr3-$(board).log \
|
||||
MEM_Arty \
|
||||
$(dst)/xlnx_mmcm.log \
|
||||
$(dst)/xlnx_axi_clock_converter.log \
|
||||
$(dst)/xlnx_ahblite_axi_bridge.log
|
||||
@ -46,7 +45,15 @@ IP_Arty: $(dst)/xlnx_proc_sys_reset.log \
|
||||
#$(dst)/xlnx_axi_dwidth_conv_64to32.log \
|
||||
#$(dst)/xlnx_axi_prtcl_conv.log
|
||||
|
||||
# Generate Memory IP Blocks
|
||||
.PHONY: MEM_VCU MEM_Arty
|
||||
MEM_VCU:
|
||||
$(MAKE) $(dst)/xlnx_ddr4-$(board).log
|
||||
MEM_Arty:
|
||||
$(MAKE) $(dst)/xlnx_ddr3-$(board).log
|
||||
|
||||
# Copy files and make necessary modifications
|
||||
.PHONY: PreProcessFiles
|
||||
PreProcessFiles:
|
||||
$(MAKE) -C ../../sim deriv
|
||||
rm -rf ../src/CopiedFiles_do_not_add_to_repo/
|
||||
@ -63,18 +70,24 @@ PreProcessFiles:
|
||||
sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
|
||||
sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/ram1p1rwbe.sv
|
||||
|
||||
# Generate Individual IP Blocks
|
||||
$(dst)/%.log: %.tcl
|
||||
mkdir -p IP
|
||||
cd IP;\
|
||||
vivado -mode batch -source ../$*.tcl | tee $*.log
|
||||
|
||||
# Clean
|
||||
.PHONY: cleanIP cleanLogs cleanFPGA cleanAll
|
||||
cleanIP:
|
||||
rm -rf IP
|
||||
|
||||
cleanLogs:
|
||||
rm -rf *.jou *.log
|
||||
|
||||
cleanFPGA:
|
||||
rm -rf WallyFPGA.* reports sim .Xil
|
||||
|
||||
cleanAll: cleanIP cleanLogs cleanFPGA
|
||||
|
||||
# Aliases
|
||||
.PHONY: arty artya7 VCU118 VCU108
|
||||
arty artya7: ArtyA7
|
||||
VCU118: vcu118
|
||||
VCU108: vcu108
|
||||
|
||||
@ -1,3 +1,8 @@
|
||||
# imperas.ic
|
||||
# Initialization file for ImperasDV lock step simulation
|
||||
# David_Harris@hmc.edu 15 August 2024
|
||||
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
#--mpdconsole
|
||||
#--gdbconsole
|
||||
#--showoverrides
|
||||
|
||||
@ -159,11 +159,11 @@ module csrc import cvw::*; #(parameter cvw_t P) (
|
||||
if (P.XLEN==64) begin // 64-bit counter reads
|
||||
// Veri lator doesn't realize this only occurs for XLEN=64
|
||||
/* verilator lint_off WIDTH */
|
||||
if (CSRAdrM == TIME) CSRCReadValM = MTIME_CLINT; // TIME register is a shadow of the memory-mapped MTIME from the CLINT
|
||||
if (CSRAdrM == TIME & ~CSRWriteM) CSRCReadValM = MTIME_CLINT; // TIME register is a shadow of the memory-mapped MTIME from the CLINT
|
||||
/* verilator lint_on WIDTH */
|
||||
else if (CSRAdrM >= MHPMCOUNTERBASE & CSRAdrM < MHPMCOUNTERBASE+P.COUNTERS & CSRAdrM != MTIME)
|
||||
CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
|
||||
else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM < HPMCOUNTERBASE+P.COUNTERS)
|
||||
else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM < HPMCOUNTERBASE+P.COUNTERS & ~CSRWriteM) // read-only
|
||||
CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
|
||||
else begin
|
||||
CSRCReadValM = '0;
|
||||
@ -172,16 +172,16 @@ module csrc import cvw::*; #(parameter cvw_t P) (
|
||||
end else begin // 32-bit counter reads
|
||||
// Veril ator doesn't realize this only occurs for XLEN=32
|
||||
/* verilator lint_off WIDTH */
|
||||
if (CSRAdrM == TIME) CSRCReadValM = MTIME_CLINT[31:0];// TIME register is a shadow of the memory-mapped MTIME from the CLINT
|
||||
else if (CSRAdrM == TIMEH) CSRCReadValM = MTIME_CLINT[63:32];
|
||||
if (CSRAdrM == TIME & ~CSRWriteM) CSRCReadValM = MTIME_CLINT[31:0];// TIME register is a shadow of the memory-mapped MTIME from the CLINT
|
||||
else if (CSRAdrM == TIMEH & ~CSRWriteM) CSRCReadValM = MTIME_CLINT[63:32];
|
||||
/* verilator lint_on WIDTH */
|
||||
else if (CSRAdrM >= MHPMCOUNTERBASE & CSRAdrM < MHPMCOUNTERBASE+P.COUNTERS & CSRAdrM != MTIME)
|
||||
CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
|
||||
else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM < HPMCOUNTERBASE+P.COUNTERS)
|
||||
else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM < HPMCOUNTERBASE+P.COUNTERS & ~CSRWriteM) // read-only
|
||||
CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
|
||||
else if (CSRAdrM >= MHPMCOUNTERHBASE & CSRAdrM < MHPMCOUNTERHBASE+P.COUNTERS & CSRAdrM != MTIMEH)
|
||||
CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM];
|
||||
else if (CSRAdrM >= HPMCOUNTERHBASE & CSRAdrM < HPMCOUNTERHBASE+P.COUNTERS)
|
||||
else if (CSRAdrM >= HPMCOUNTERHBASE & CSRAdrM < HPMCOUNTERHBASE+P.COUNTERS & ~CSRWriteM) // read-only
|
||||
CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM];
|
||||
else begin
|
||||
CSRCReadValM = '0;
|
||||
|
||||
34
tests/fp/Makefile
Executable file
34
tests/fp/Makefile
Executable file
@ -0,0 +1,34 @@
|
||||
# Jordan Carlin, jcarlin@hmc.edu, August 2024
|
||||
# Testfloat vector Makefile for CORE-V-Wally
|
||||
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
SOFTFLOAT_DIR := ${WALLY}/addins/SoftFloat-3e/build/Linux-x86_64-GCC
|
||||
TESTFLOAT_DIR := ${WALLY}/addins/TestFloat-3e/build/Linux-x86_64-GCC
|
||||
|
||||
.PHONY: all softfloat testfloat vectors combined_IF_vectors clean
|
||||
|
||||
all: vectors combined_IF_vectors
|
||||
|
||||
softfloat: ${SOFTFLOAT_DIR}/softfloat.a
|
||||
|
||||
testfloat: ${TESTFLOAT_DIR}/testfloat
|
||||
|
||||
vectors: testfloat
|
||||
$(MAKE) -C ${WALLY}/tests/fp/vectors
|
||||
|
||||
combined_IF_vectors: ${WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/M/src vectors
|
||||
cd ${WALLY}/tests/fp/combined_IF_vectors \
|
||||
&& ./create_IF_vectors.sh
|
||||
|
||||
clean:
|
||||
$(MAKE) -C ${WALLY}/tests/fp/vectors clean
|
||||
rm -f ${WALLY}/tests/fp/combined_IF_vectors/IF_vectors/*.tv
|
||||
|
||||
${SOFTFLOAT_DIR}/softfloat.a:
|
||||
$(MAKE) -C ${SOFTFLOAT_DIR}
|
||||
|
||||
${TESTFLOAT_DIR}/testfloat: ${SOFTFLOAT_DIR}/softfloat.a
|
||||
$(MAKE) -C ${TESTFLOAT_DIR}
|
||||
|
||||
${WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/M/src:
|
||||
@$(error "riscv-arch-tests must be generated first. Run make from $$WALLY")
|
||||
@ -1,187 +1,171 @@
|
||||
james.stine@okstate.edu 14 Jan 2022
|
||||
|
||||
These are the testvectors (TV) to test the floating-point units using
|
||||
These are the testvectors (TV) to test the floating-point unit using
|
||||
Berkeley TestFloat written originally by John Hauser. TestFloat
|
||||
requires both TestFloat and SoftFloat.
|
||||
|
||||
The locations at time of this README is found here:
|
||||
The locations of these tools at time of this README is found here:
|
||||
TestFloat-3e: http://www.jhauser.us/arithmetic/TestFloat.html
|
||||
SoftFloat-3e: http://www.jhauser.us/arithmetic/SoftFloat.html
|
||||
|
||||
These files have been compiled on a x86_64 environment by going into
|
||||
the build/Linux-x86_64-GCC directory and typing make. A script
|
||||
createX.sh (e.g., create_vectors32.sh) has been included that create
|
||||
the TV for each rounding mode and operation. These scripts must be
|
||||
run in the build directory of TestFloat.
|
||||
These tools have been compiled on a x86_64 environment by going into
|
||||
their respective build/Linux-x86_64-GCC directories and running make.
|
||||
|
||||
A set of scripts is also include that runs everything from the
|
||||
baseline directory. Please change the BUILD and OUTPUT variable to
|
||||
change your baseline program where its compiled and where you want to
|
||||
output the vectors. By default, the vectors are output into the
|
||||
vectors subdirectory.
|
||||
The makefile in the vectors subdirectory of this directory will generate TV
|
||||
for each rounding mode and operation. It also puts an underscore between each
|
||||
vector instead of a space to allow SystemVerilog readmemh to read correctly.
|
||||
|
||||
After each TV has been created a script (included) is run called
|
||||
undy.sh that puts an underscore between vector to allow SystemVerilog
|
||||
readmemh to read correctly.
|
||||
|
||||
./undy.sh file.tv
|
||||
|
||||
To remove all the underscores from all the TV files, one can run the
|
||||
command that will add underscores appropriately to all the files.
|
||||
|
||||
cd vectors
|
||||
../undy.sh \*
|
||||
|
||||
Note: due to size, the fxx_fma_xx.tv vectors are not included.
|
||||
However, they can easily be created with the create scripts.
|
||||
The makefile at the top level of this directory will compile SoftFloat and
|
||||
TestFloat and then generate all of the TVs. It also generates TVs for the
|
||||
combined integer floating-point divider.
|
||||
|
||||
Although not needed, a case.sh script is included to change the case
|
||||
of the hex output. This is for those that do not like to see
|
||||
hexadecimal capitalized :P.
|
||||
hexadecimal capitalized :P.
|
||||
|
||||
46464 185856 836352 f16_add_rd.tv
|
||||
46464 185856 836352 f16_add_rne.tv
|
||||
46464 185856 836352 f16_add_ru.tv
|
||||
46464 185856 836352 f16_add_rz.tv
|
||||
46464 185856 836352 f16_div_rd.tv
|
||||
46464 185856 836352 f16_div_rne.tv
|
||||
46464 185856 836352 f16_div_ru.tv
|
||||
46464 185856 836352 f16_div_rz.tv
|
||||
46464 185856 836352 f16_mul_rd.tv
|
||||
46464 185856 836352 f16_mul_rne.tv
|
||||
46464 185856 836352 f16_mul_ru.tv
|
||||
46464 185856 836352 f16_mul_rz.tv
|
||||
408 1224 5304 f16_sqrt_rd.tv
|
||||
408 1224 5304 f16_sqrt_rne.tv
|
||||
408 1224 5304 f16_sqrt_ru.tv
|
||||
408 1224 5304 f16_sqrt_rz.tv
|
||||
46464 185856 836352 f16_sub_rd.tv
|
||||
46464 185856 836352 f16_sub_rne.tv
|
||||
46464 185856 836352 f16_sub_ru.tv
|
||||
46464 185856 836352 f16_sub_rz.tv
|
||||
46464 185856 1393920 f32_add_rd.tv
|
||||
46464 185856 1393920 f32_add_rne.tv
|
||||
46464 185856 1393920 f32_add_ru.tv
|
||||
46464 185856 1393920 f32_add_rz.tv
|
||||
46464 185856 1068672 f32_cmp_eq_signaling.tv
|
||||
46464 185856 1068672 f32_cmp_eq.tv
|
||||
46464 185856 1068672 f32_cmp_le_quiet.tv
|
||||
46464 185856 1068672 f32_cmp_le.tv
|
||||
46464 185856 1068672 f32_cmp_lt_quiet.tv
|
||||
46464 185856 1068672 f32_cmp_lt.tv
|
||||
46464 185856 1393920 f32_div_rd.tv
|
||||
46464 185856 1393920 f32_div_rne.tv
|
||||
46464 185856 1393920 f32_div_ru.tv
|
||||
46464 185856 1393920 f32_div_rz.tv
|
||||
600 1800 17400 f32_f64_rd.tv
|
||||
600 1800 17400 f32_f64_rne.tv
|
||||
600 1800 17400 f32_f64_ru.tv
|
||||
600 1800 17400 f32_f64_rz.tv
|
||||
600 1800 12600 f32_i32_rd.tv
|
||||
600 1800 12600 f32_i32_rne.tv
|
||||
600 1800 12600 f32_i32_ru.tv
|
||||
600 1800 12600 f32_i32_rz.tv
|
||||
600 1800 17400 f32_i64_rd.tv
|
||||
600 1800 17400 f32_i64_rne.tv
|
||||
600 1800 17400 f32_i64_ru.tv
|
||||
600 1800 17400 f32_i64_rz.tv
|
||||
46464 185856 1393920 f32_mul_rd.tv
|
||||
46464 185856 1393920 f32_mul_rne.tv
|
||||
46464 185856 1393920 f32_mul_ru.tv
|
||||
46464 185856 1393920 f32_mul_rz.tv
|
||||
600 1800 12600 f32_sqrt_rd.tv
|
||||
600 1800 12600 f32_sqrt_rne.tv
|
||||
600 1800 12600 f32_sqrt_ru.tv
|
||||
600 1800 12600 f32_sqrt_rz.tv
|
||||
46464 185856 1393920 f32_sub_rd.tv
|
||||
46464 185856 1393920 f32_sub_rne.tv
|
||||
46464 185856 1393920 f32_sub_ru.tv
|
||||
46464 185856 1393920 f32_sub_rz.tv
|
||||
600 1800 12600 f32_ui32_rd.tv
|
||||
600 1800 12600 f32_ui32_rne.tv
|
||||
600 1800 12600 f32_ui32_ru.tv
|
||||
600 1800 12600 f32_ui32_rz.tv
|
||||
600 1800 17400 f32_ui64_rd.tv
|
||||
600 1800 17400 f32_ui64_rne.tv
|
||||
600 1800 17400 f32_ui64_ru.tv
|
||||
600 1800 17400 f32_ui64_rz.tv
|
||||
46464 185856 2509056 f64_add_rd.tv
|
||||
46464 185856 2509056 f64_add_rne.tv
|
||||
46464 185856 2509056 f64_add_ru.tv
|
||||
46464 185856 2509056 f64_add_rz.tv
|
||||
46464 185856 1812096 f64_cmp_eq_signaling.tv
|
||||
46464 185856 1812096 f64_cmp_eq.tv
|
||||
46464 185856 1812096 f64_cmp_le_quiet.tv
|
||||
46464 185856 1812096 f64_cmp_le.tv
|
||||
46464 185856 1812096 f64_cmp_lt_quiet.tv
|
||||
46464 185856 1812096 f64_cmp_lt.tv
|
||||
46464 185856 2509056 f64_div_rd.tv
|
||||
46464 185856 2509056 f64_div_rne.tv
|
||||
46464 185856 2509056 f64_div_ru.tv
|
||||
46464 185856 2509056 f64_div_rz.tv
|
||||
768 2304 22272 f64_f32_rd.tv
|
||||
768 2304 22272 f64_f32_rne.tv
|
||||
768 2304 22272 f64_f32_ru.tv
|
||||
768 2304 22272 f64_f32_rz.tv
|
||||
768 2304 22272 f64_i32_rd.tv
|
||||
768 2304 22272 f64_i32_rne.tv
|
||||
768 2304 22272 f64_i32_ru.tv
|
||||
768 2304 22272 f64_i32_rz.tv
|
||||
768 2304 28416 f64_i64_rd.tv
|
||||
768 2304 28416 f64_i64_rne.tv
|
||||
768 2304 28416 f64_i64_ru.tv
|
||||
768 2304 28416 f64_i64_rz.tv
|
||||
46464 185856 2509056 f64_mul_rd.tv
|
||||
46464 185856 2509056 f64_mul_rne.tv
|
||||
46464 185856 2509056 f64_mul_ru.tv
|
||||
46464 185856 2509056 f64_mul_rz.tv
|
||||
768 2304 28416 f64_sqrt_rd.tv
|
||||
768 2304 28416 f64_sqrt_rne.tv
|
||||
768 2304 28416 f64_sqrt_ru.tv
|
||||
768 2304 28416 f64_sqrt_rz.tv
|
||||
46464 185856 2509056 f64_sub_rd.tv
|
||||
46464 185856 2509056 f64_sub_rne.tv
|
||||
46464 185856 2509056 f64_sub_ru.tv
|
||||
46464 185856 2509056 f64_sub_rz.tv
|
||||
768 2304 22272 f64_ui32_rd.tv
|
||||
768 2304 22272 f64_ui32_rne.tv
|
||||
768 2304 22272 f64_ui32_ru.tv
|
||||
768 2304 22272 f64_ui32_rz.tv
|
||||
768 2304 28416 f64_ui64_rd.tv
|
||||
768 2304 28416 f64_ui64_rne.tv
|
||||
768 2304 28416 f64_ui64_ru.tv
|
||||
768 2304 28416 f64_ui64_rz.tv
|
||||
372 1116 7812 i32_f32_rd.tv
|
||||
372 1116 7812 i32_f32_rne.tv
|
||||
372 1116 7812 i32_f32_ru.tv
|
||||
372 1116 7812 i32_f32_rz.tv
|
||||
372 1116 10788 i32_f64_rd.tv
|
||||
372 1116 10788 i32_f64_rne.tv
|
||||
372 1116 10788 i32_f64_ru.tv
|
||||
372 1116 10788 i32_f64_rz.tv
|
||||
756 2268 21924 i64_f32_rd.tv
|
||||
756 2268 21924 i64_f32_rne.tv
|
||||
756 2268 21924 i64_f32_ru.tv
|
||||
756 2268 21924 i64_f32_rz.tv
|
||||
756 2268 27972 i64_f64_rd.tv
|
||||
756 2268 27972 i64_f64_rne.tv
|
||||
756 2268 27972 i64_f64_ru.tv
|
||||
756 2268 27972 i64_f64_rz.tv
|
||||
372 1116 7812 ui32_f32_rd.tv
|
||||
372 1116 7812 ui32_f32_rne.tv
|
||||
372 1116 7812 ui32_f32_ru.tv
|
||||
372 1116 7812 ui32_f32_rz.tv
|
||||
372 1116 10788 ui32_f64_rd.tv
|
||||
372 1116 10788 ui32_f64_rne.tv
|
||||
372 1116 10788 ui32_f64_ru.tv
|
||||
372 1116 10788 ui32_f64_rz.tv
|
||||
756 2268 21924 ui64_f32_rd.tv
|
||||
756 2268 21924 ui64_f32_rne.tv
|
||||
756 2268 21924 ui64_f32_ru.tv
|
||||
756 2268 21924 ui64_f32_rz.tv
|
||||
756 2268 27972 ui64_f64_rd.tv
|
||||
756 2268 27972 ui64_f64_rne.tv
|
||||
756 2268 27972 ui64_f64_ru.tv
|
||||
756 2268 27972 ui64_f64_rz.tv
|
||||
2840352 11308896 94651296 total
|
||||
46464 185856 836352 f16_add_rd.tv
|
||||
46464 185856 836352 f16_add_rne.tv
|
||||
46464 185856 836352 f16_add_ru.tv
|
||||
46464 185856 836352 f16_add_rz.tv
|
||||
46464 185856 836352 f16_div_rd.tv
|
||||
46464 185856 836352 f16_div_rne.tv
|
||||
46464 185856 836352 f16_div_ru.tv
|
||||
46464 185856 836352 f16_div_rz.tv
|
||||
46464 185856 836352 f16_mul_rd.tv
|
||||
46464 185856 836352 f16_mul_rne.tv
|
||||
46464 185856 836352 f16_mul_ru.tv
|
||||
46464 185856 836352 f16_mul_rz.tv
|
||||
408 1224 5304 f16_sqrt_rd.tv
|
||||
408 1224 5304 f16_sqrt_rne.tv
|
||||
408 1224 5304 f16_sqrt_ru.tv
|
||||
408 1224 5304 f16_sqrt_rz.tv
|
||||
46464 185856 836352 f16_sub_rd.tv
|
||||
46464 185856 836352 f16_sub_rne.tv
|
||||
46464 185856 836352 f16_sub_ru.tv
|
||||
46464 185856 836352 f16_sub_rz.tv
|
||||
46464 185856 1393920 f32_add_rd.tv
|
||||
46464 185856 1393920 f32_add_rne.tv
|
||||
46464 185856 1393920 f32_add_ru.tv
|
||||
46464 185856 1393920 f32_add_rz.tv
|
||||
46464 185856 1068672 f32_cmp_eq_signaling.tv
|
||||
46464 185856 1068672 f32_cmp_eq.tv
|
||||
46464 185856 1068672 f32_cmp_le_quiet.tv
|
||||
46464 185856 1068672 f32_cmp_le.tv
|
||||
46464 185856 1068672 f32_cmp_lt_quiet.tv
|
||||
46464 185856 1068672 f32_cmp_lt.tv
|
||||
46464 185856 1393920 f32_div_rd.tv
|
||||
46464 185856 1393920 f32_div_rne.tv
|
||||
46464 185856 1393920 f32_div_ru.tv
|
||||
46464 185856 1393920 f32_div_rz.tv
|
||||
600 1800 17400 f32_f64_rd.tv
|
||||
600 1800 17400 f32_f64_rne.tv
|
||||
600 1800 17400 f32_f64_ru.tv
|
||||
600 1800 17400 f32_f64_rz.tv
|
||||
600 1800 12600 f32_i32_rd.tv
|
||||
600 1800 12600 f32_i32_rne.tv
|
||||
600 1800 12600 f32_i32_ru.tv
|
||||
600 1800 12600 f32_i32_rz.tv
|
||||
600 1800 17400 f32_i64_rd.tv
|
||||
600 1800 17400 f32_i64_rne.tv
|
||||
600 1800 17400 f32_i64_ru.tv
|
||||
600 1800 17400 f32_i64_rz.tv
|
||||
46464 185856 1393920 f32_mul_rd.tv
|
||||
46464 185856 1393920 f32_mul_rne.tv
|
||||
46464 185856 1393920 f32_mul_ru.tv
|
||||
46464 185856 1393920 f32_mul_rz.tv
|
||||
600 1800 12600 f32_sqrt_rd.tv
|
||||
600 1800 12600 f32_sqrt_rne.tv
|
||||
600 1800 12600 f32_sqrt_ru.tv
|
||||
600 1800 12600 f32_sqrt_rz.tv
|
||||
46464 185856 1393920 f32_sub_rd.tv
|
||||
46464 185856 1393920 f32_sub_rne.tv
|
||||
46464 185856 1393920 f32_sub_ru.tv
|
||||
46464 185856 1393920 f32_sub_rz.tv
|
||||
600 1800 12600 f32_ui32_rd.tv
|
||||
600 1800 12600 f32_ui32_rne.tv
|
||||
600 1800 12600 f32_ui32_ru.tv
|
||||
600 1800 12600 f32_ui32_rz.tv
|
||||
600 1800 17400 f32_ui64_rd.tv
|
||||
600 1800 17400 f32_ui64_rne.tv
|
||||
600 1800 17400 f32_ui64_ru.tv
|
||||
600 1800 17400 f32_ui64_rz.tv
|
||||
46464 185856 2509056 f64_add_rd.tv
|
||||
46464 185856 2509056 f64_add_rne.tv
|
||||
46464 185856 2509056 f64_add_ru.tv
|
||||
46464 185856 2509056 f64_add_rz.tv
|
||||
46464 185856 1812096 f64_cmp_eq_signaling.tv
|
||||
46464 185856 1812096 f64_cmp_eq.tv
|
||||
46464 185856 1812096 f64_cmp_le_quiet.tv
|
||||
46464 185856 1812096 f64_cmp_le.tv
|
||||
46464 185856 1812096 f64_cmp_lt_quiet.tv
|
||||
46464 185856 1812096 f64_cmp_lt.tv
|
||||
46464 185856 2509056 f64_div_rd.tv
|
||||
46464 185856 2509056 f64_div_rne.tv
|
||||
46464 185856 2509056 f64_div_ru.tv
|
||||
46464 185856 2509056 f64_div_rz.tv
|
||||
768 2304 22272 f64_f32_rd.tv
|
||||
768 2304 22272 f64_f32_rne.tv
|
||||
768 2304 22272 f64_f32_ru.tv
|
||||
768 2304 22272 f64_f32_rz.tv
|
||||
768 2304 22272 f64_i32_rd.tv
|
||||
768 2304 22272 f64_i32_rne.tv
|
||||
768 2304 22272 f64_i32_ru.tv
|
||||
768 2304 22272 f64_i32_rz.tv
|
||||
768 2304 28416 f64_i64_rd.tv
|
||||
768 2304 28416 f64_i64_rne.tv
|
||||
768 2304 28416 f64_i64_ru.tv
|
||||
768 2304 28416 f64_i64_rz.tv
|
||||
46464 185856 2509056 f64_mul_rd.tv
|
||||
46464 185856 2509056 f64_mul_rne.tv
|
||||
46464 185856 2509056 f64_mul_ru.tv
|
||||
46464 185856 2509056 f64_mul_rz.tv
|
||||
768 2304 28416 f64_sqrt_rd.tv
|
||||
768 2304 28416 f64_sqrt_rne.tv
|
||||
768 2304 28416 f64_sqrt_ru.tv
|
||||
768 2304 28416 f64_sqrt_rz.tv
|
||||
46464 185856 2509056 f64_sub_rd.tv
|
||||
46464 185856 2509056 f64_sub_rne.tv
|
||||
46464 185856 2509056 f64_sub_ru.tv
|
||||
46464 185856 2509056 f64_sub_rz.tv
|
||||
768 2304 22272 f64_ui32_rd.tv
|
||||
768 2304 22272 f64_ui32_rne.tv
|
||||
768 2304 22272 f64_ui32_ru.tv
|
||||
768 2304 22272 f64_ui32_rz.tv
|
||||
768 2304 28416 f64_ui64_rd.tv
|
||||
768 2304 28416 f64_ui64_rne.tv
|
||||
768 2304 28416 f64_ui64_ru.tv
|
||||
768 2304 28416 f64_ui64_rz.tv
|
||||
372 1116 7812 i32_f32_rd.tv
|
||||
372 1116 7812 i32_f32_rne.tv
|
||||
372 1116 7812 i32_f32_ru.tv
|
||||
372 1116 7812 i32_f32_rz.tv
|
||||
372 1116 10788 i32_f64_rd.tv
|
||||
372 1116 10788 i32_f64_rne.tv
|
||||
372 1116 10788 i32_f64_ru.tv
|
||||
372 1116 10788 i32_f64_rz.tv
|
||||
756 2268 21924 i64_f32_rd.tv
|
||||
756 2268 21924 i64_f32_rne.tv
|
||||
756 2268 21924 i64_f32_ru.tv
|
||||
756 2268 21924 i64_f32_rz.tv
|
||||
756 2268 27972 i64_f64_rd.tv
|
||||
756 2268 27972 i64_f64_rne.tv
|
||||
756 2268 27972 i64_f64_ru.tv
|
||||
756 2268 27972 i64_f64_rz.tv
|
||||
372 1116 7812 ui32_f32_rd.tv
|
||||
372 1116 7812 ui32_f32_rne.tv
|
||||
372 1116 7812 ui32_f32_ru.tv
|
||||
372 1116 7812 ui32_f32_rz.tv
|
||||
372 1116 10788 ui32_f64_rd.tv
|
||||
372 1116 10788 ui32_f64_rne.tv
|
||||
372 1116 10788 ui32_f64_ru.tv
|
||||
372 1116 10788 ui32_f64_rz.tv
|
||||
756 2268 21924 ui64_f32_rd.tv
|
||||
756 2268 21924 ui64_f32_rne.tv
|
||||
756 2268 21924 ui64_f32_ru.tv
|
||||
756 2268 21924 ui64_f32_rz.tv
|
||||
756 2268 27972 ui64_f64_rd.tv
|
||||
756 2268 27972 ui64_f64_rne.tv
|
||||
756 2268 27972 ui64_f64_ru.tv
|
||||
756 2268 27972 ui64_f64_rz.tv
|
||||
2840352 11308896 94651296 total
|
||||
|
||||
|
||||
@ -1,8 +0,0 @@
|
||||
#!/bin/sh
|
||||
|
||||
mkdir -p vectors
|
||||
./create_vectors.sh
|
||||
./remove_spaces.sh
|
||||
|
||||
# to create tvs for evaluation of combined IFdivsqrt
|
||||
cd combined_IF_vectors; ./create_IF_vectors.sh
|
||||
@ -1,483 +0,0 @@
|
||||
#!/bin/sh
|
||||
BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC"
|
||||
OUTPUT="./vectors"
|
||||
echo "Creating ui32_to_f16 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui32_to_f16 > $OUTPUT/ui32_to_f16_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui32_to_f16 > $OUTPUT/ui32_to_f16_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui32_to_f16 > $OUTPUT/ui32_to_f16_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui32_to_f16 > $OUTPUT/ui32_to_f16_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui32_to_f16 > $OUTPUT/ui32_to_f16_rnm.tv
|
||||
echo "Creating ui32_to_f32 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui32_to_f32 > $OUTPUT/ui32_to_f32_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui32_to_f32 > $OUTPUT/ui32_to_f32_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui32_to_f32 > $OUTPUT/ui32_to_f32_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui32_to_f32 > $OUTPUT/ui32_to_f32_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui32_to_f32 > $OUTPUT/ui32_to_f32_rnm.tv
|
||||
echo "Creating ui32_to_f64 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui32_to_f64 > $OUTPUT/ui32_to_f64_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui32_to_f64 > $OUTPUT/ui32_to_f64_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui32_to_f64 > $OUTPUT/ui32_to_f64_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui32_to_f64 > $OUTPUT/ui32_to_f64_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui32_to_f64 > $OUTPUT/ui32_to_f64_rnm.tv
|
||||
echo "Creating ui32_to_f128 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui32_to_f128 > $OUTPUT/ui32_to_f128_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui32_to_f128 > $OUTPUT/ui32_to_f128_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui32_to_f128 > $OUTPUT/ui32_to_f128_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui32_to_f128 > $OUTPUT/ui32_to_f128_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui32_to_f128 > $OUTPUT/ui32_to_f128_rnm.tv
|
||||
echo "Creating ui64_to_f16 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui64_to_f16 > $OUTPUT/ui64_to_f16_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui64_to_f16 > $OUTPUT/ui64_to_f16_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui64_to_f16 > $OUTPUT/ui64_to_f16_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui64_to_f16 > $OUTPUT/ui64_to_f16_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui64_to_f16 > $OUTPUT/ui64_to_f16_rnm.tv
|
||||
echo "Creating ui64_to_f32 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui64_to_f32 > $OUTPUT/ui64_to_f32_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui64_to_f32 > $OUTPUT/ui64_to_f32_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui64_to_f32 > $OUTPUT/ui64_to_f32_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui64_to_f32 > $OUTPUT/ui64_to_f32_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui64_to_f32 > $OUTPUT/ui64_to_f32_rnm.tv
|
||||
echo "Creating ui64_to_f64 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui64_to_f64 > $OUTPUT/ui64_to_f64_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui64_to_f64 > $OUTPUT/ui64_to_f64_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui64_to_f64 > $OUTPUT/ui64_to_f64_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui64_to_f64 > $OUTPUT/ui64_to_f64_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui64_to_f64 > $OUTPUT/ui64_to_f64_rnm.tv
|
||||
echo "Creating ui64_to_f128 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui64_to_f128 > $OUTPUT/ui64_to_f128_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui64_to_f128 > $OUTPUT/ui64_to_f128_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui64_to_f128 > $OUTPUT/ui64_to_f128_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui64_to_f128 > $OUTPUT/ui64_to_f128_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui64_to_f128 > $OUTPUT/ui64_to_f128_rnm.tv
|
||||
echo "Creating i32_to_f16 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i32_to_f16 > $OUTPUT/i32_to_f16_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i32_to_f16 > $OUTPUT/i32_to_f16_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax i32_to_f16 > $OUTPUT/i32_to_f16_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin i32_to_f16 > $OUTPUT/i32_to_f16_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i32_to_f16 > $OUTPUT/i32_to_f16_rnm.tv
|
||||
echo "Creating i32_to_f32 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i32_to_f32 > $OUTPUT/i32_to_f32_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i32_to_f32 > $OUTPUT/i32_to_f32_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax i32_to_f32 > $OUTPUT/i32_to_f32_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin i32_to_f32 > $OUTPUT/i32_to_f32_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i32_to_f32 > $OUTPUT/i32_to_f32_rnm.tv
|
||||
echo "Creating i32_to_f64 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i32_to_f64 > $OUTPUT/i32_to_f64_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i32_to_f64 > $OUTPUT/i32_to_f64_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax i32_to_f64 > $OUTPUT/i32_to_f64_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin i32_to_f64 > $OUTPUT/i32_to_f64_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i32_to_f64 > $OUTPUT/i32_to_f64_rnm.tv
|
||||
echo "Creating i32_to_f128 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i32_to_f128 > $OUTPUT/i32_to_f128_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i32_to_f128 > $OUTPUT/i32_to_f128_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax i32_to_f128 > $OUTPUT/i32_to_f128_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin i32_to_f128 > $OUTPUT/i32_to_f128_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i32_to_f128 > $OUTPUT/i32_to_f128_rnm.tv
|
||||
echo "Creating i64_to_f16 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i64_to_f16 > $OUTPUT/i64_to_f16_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i64_to_f16 > $OUTPUT/i64_to_f16_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax i64_to_f16 > $OUTPUT/i64_to_f16_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin i64_to_f16 > $OUTPUT/i64_to_f16_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i64_to_f16 > $OUTPUT/i64_to_f16_rnm.tv
|
||||
echo "Creating i64_to_f32 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i64_to_f32 > $OUTPUT/i64_to_f32_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i64_to_f32 > $OUTPUT/i64_to_f32_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax i64_to_f32 > $OUTPUT/i64_to_f32_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin i64_to_f32 > $OUTPUT/i64_to_f32_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i64_to_f32 > $OUTPUT/i64_to_f32_rnm.tv
|
||||
echo "Creating i64_to_f64 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i64_to_f64 > $OUTPUT/i64_to_f64_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i64_to_f64 > $OUTPUT/i64_to_f64_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax i64_to_f64 > $OUTPUT/i64_to_f64_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin i64_to_f64 > $OUTPUT/i64_to_f64_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i64_to_f64 > $OUTPUT/i64_to_f64_rnm.tv
|
||||
echo "Creating i64_to_f128 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i64_to_f128 > $OUTPUT/i64_to_f128_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i64_to_f128 > $OUTPUT/i64_to_f128_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax i64_to_f128 > $OUTPUT/i64_to_f128_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin i64_to_f128 > $OUTPUT/i64_to_f128_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i64_to_f128 > $OUTPUT/i64_to_f128_rnm.tv
|
||||
echo "Creating f16_to_ui32 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f16_to_ui32 > $OUTPUT/f16_to_ui32_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f16_to_ui32 > $OUTPUT/f16_to_ui32_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f16_to_ui32 > $OUTPUT/f16_to_ui32_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f16_to_ui32 > $OUTPUT/f16_to_ui32_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f16_to_ui32 > $OUTPUT/f16_to_ui32_rnm.tv
|
||||
echo "Creating f32_to_ui32 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f32_to_ui32 > $OUTPUT/f32_to_ui32_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f32_to_ui32 > $OUTPUT/f32_to_ui32_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f32_to_ui32 > $OUTPUT/f32_to_ui32_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f32_to_ui32 > $OUTPUT/f32_to_ui32_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f32_to_ui32 > $OUTPUT/f32_to_ui32_rnm.tv
|
||||
echo "Creating f64_to_ui32 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f64_to_ui32 > $OUTPUT/f64_to_ui32_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f64_to_ui32 > $OUTPUT/f64_to_ui32_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f64_to_ui32 > $OUTPUT/f64_to_ui32_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f64_to_ui32 > $OUTPUT/f64_to_ui32_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f64_to_ui32 > $OUTPUT/f64_to_ui32_rnm.tv
|
||||
echo "Creating f128_to_ui32 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f128_to_ui32 > $OUTPUT/f128_to_ui32_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f128_to_ui32 > $OUTPUT/f128_to_ui32_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f128_to_ui32 > $OUTPUT/f128_to_ui32_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f128_to_ui32 > $OUTPUT/f128_to_ui32_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f128_to_ui32 > $OUTPUT/f128_to_ui32_rnm.tv
|
||||
echo "Creating f16_to_ui64 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f16_to_ui64 > $OUTPUT/f16_to_ui64_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f16_to_ui64 > $OUTPUT/f16_to_ui64_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f16_to_ui64 > $OUTPUT/f16_to_ui64_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f16_to_ui64 > $OUTPUT/f16_to_ui64_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f16_to_ui64 > $OUTPUT/f16_to_ui64_rnm.tv
|
||||
echo "Creating f32_to_ui64 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f32_to_ui64 > $OUTPUT/f32_to_ui64_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f32_to_ui64 > $OUTPUT/f32_to_ui64_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f32_to_ui64 > $OUTPUT/f32_to_ui64_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f32_to_ui64 > $OUTPUT/f32_to_ui64_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f32_to_ui64 > $OUTPUT/f32_to_ui64_rnm.tv
|
||||
echo "Creating f64_to_ui64 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f64_to_ui64 > $OUTPUT/f64_to_ui64_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f64_to_ui64 > $OUTPUT/f64_to_ui64_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f64_to_ui64 > $OUTPUT/f64_to_ui64_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f64_to_ui64 > $OUTPUT/f64_to_ui64_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f64_to_ui64 > $OUTPUT/f64_to_ui64_rnm.tv
|
||||
echo "Creating f128_to_ui64 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f128_to_ui64 > $OUTPUT/f128_to_ui64_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f128_to_ui64 > $OUTPUT/f128_to_ui64_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f128_to_ui64 > $OUTPUT/f128_to_ui64_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f128_to_ui64 > $OUTPUT/f128_to_ui64_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f128_to_ui64 > $OUTPUT/f128_to_ui64_rnm.tv
|
||||
echo "Creating f16_to_i32 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f16_to_i32 > $OUTPUT/f16_to_i32_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f16_to_i32 > $OUTPUT/f16_to_i32_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f16_to_i32 > $OUTPUT/f16_to_i32_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f16_to_i32 > $OUTPUT/f16_to_i32_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f16_to_i32 > $OUTPUT/f16_to_i32_rnm.tv
|
||||
echo "Creating f32_to_i32 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f32_to_i32 > $OUTPUT/f32_to_i32_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f32_to_i32 > $OUTPUT/f32_to_i32_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f32_to_i32 > $OUTPUT/f32_to_i32_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f32_to_i32 > $OUTPUT/f32_to_i32_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f32_to_i32 > $OUTPUT/f32_to_i32_rnm.tv
|
||||
echo "Creating f64_to_i32 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f64_to_i32 > $OUTPUT/f64_to_i32_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f64_to_i32 > $OUTPUT/f64_to_i32_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f64_to_i32 > $OUTPUT/f64_to_i32_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f64_to_i32 > $OUTPUT/f64_to_i32_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f64_to_i32 > $OUTPUT/f64_to_i32_rnm.tv
|
||||
echo "Creating f128_to_i32 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f128_to_i32 > $OUTPUT/f128_to_i32_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f128_to_i32 > $OUTPUT/f128_to_i32_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f128_to_i32 > $OUTPUT/f128_to_i32_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f128_to_i32 > $OUTPUT/f128_to_i32_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f128_to_i32 > $OUTPUT/f128_to_i32_rnm.tv
|
||||
echo "Creating f16_to_i64 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f16_to_i64 > $OUTPUT/f16_to_i64_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f16_to_i64 > $OUTPUT/f16_to_i64_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f16_to_i64 > $OUTPUT/f16_to_i64_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f16_to_i64 > $OUTPUT/f16_to_i64_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f16_to_i64 > $OUTPUT/f16_to_i64_rnm.tv
|
||||
echo "Creating f32_to_i64 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f32_to_i64 > $OUTPUT/f32_to_i64_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f32_to_i64 > $OUTPUT/f32_to_i64_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f32_to_i64 > $OUTPUT/f32_to_i64_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f32_to_i64 > $OUTPUT/f32_to_i64_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f32_to_i64 > $OUTPUT/f32_to_i64_rnm.tv
|
||||
echo "Creating f64_to_i64 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f64_to_i64 > $OUTPUT/f64_to_i64_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f64_to_i64 > $OUTPUT/f64_to_i64_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f64_to_i64 > $OUTPUT/f64_to_i64_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f64_to_i64 > $OUTPUT/f64_to_i64_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f64_to_i64 > $OUTPUT/f64_to_i64_rnm.tv
|
||||
echo "Creating f128_to_i64 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f128_to_i64 > $OUTPUT/f128_to_i64_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f128_to_i64 > $OUTPUT/f128_to_i64_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f128_to_i64 > $OUTPUT/f128_to_i64_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f128_to_i64 > $OUTPUT/f128_to_i64_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f128_to_i64 > $OUTPUT/f128_to_i64_rnm.tv
|
||||
echo "Creating f16_to_f32 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f16_to_f32 > $OUTPUT/f16_to_f32_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f16_to_f32 > $OUTPUT/f16_to_f32_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f16_to_f32 > $OUTPUT/f16_to_f32_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f16_to_f32 > $OUTPUT/f16_to_f32_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f16_to_f32 > $OUTPUT/f16_to_f32_rnm.tv
|
||||
echo "Creating f16_to_f64 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f16_to_f64 > $OUTPUT/f16_to_f64_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f16_to_f64 > $OUTPUT/f16_to_f64_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f16_to_f64 > $OUTPUT/f16_to_f64_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f16_to_f64 > $OUTPUT/f16_to_f64_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f16_to_f64 > $OUTPUT/f16_to_f64_rnm.tv
|
||||
echo "Creating f16_to_f128 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f16_to_f128 > $OUTPUT/f16_to_f128_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f16_to_f128 > $OUTPUT/f16_to_f128_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f16_to_f128 > $OUTPUT/f16_to_f128_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f16_to_f128 > $OUTPUT/f16_to_f128_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f16_to_f128 > $OUTPUT/f16_to_f128_rnm.tv
|
||||
echo "Creating f32_to_f16 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f32_to_f16 > $OUTPUT/f32_to_f16_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f32_to_f16 > $OUTPUT/f32_to_f16_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f32_to_f16 > $OUTPUT/f32_to_f16_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f32_to_f16 > $OUTPUT/f32_to_f16_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f32_to_f16 > $OUTPUT/f32_to_f16_rnm.tv
|
||||
echo "Creating f32_to_f64 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f32_to_f64 > $OUTPUT/f32_to_f64_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f32_to_f64 > $OUTPUT/f32_to_f64_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f32_to_f64 > $OUTPUT/f32_to_f64_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f32_to_f64 > $OUTPUT/f32_to_f64_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f32_to_f64 > $OUTPUT/f32_to_f64_rnm.tv
|
||||
echo "Creating f32_to_f128 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f32_to_f128 > $OUTPUT/f32_to_f128_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f32_to_f128 > $OUTPUT/f32_to_f128_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f32_to_f128 > $OUTPUT/f32_to_f128_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f32_to_f128 > $OUTPUT/f32_to_f128_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f32_to_f128 > $OUTPUT/f32_to_f128_rnm.tv
|
||||
echo "Creating f64_to_f16 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f64_to_f16 > $OUTPUT/f64_to_f16_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f64_to_f16 > $OUTPUT/f64_to_f16_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f64_to_f16 > $OUTPUT/f64_to_f16_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f64_to_f16 > $OUTPUT/f64_to_f16_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f64_to_f16 > $OUTPUT/f64_to_f16_rnm.tv
|
||||
echo "Creating f64_to_f32 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f64_to_f32 > $OUTPUT/f64_to_f32_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f64_to_f32 > $OUTPUT/f64_to_f32_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f64_to_f32 > $OUTPUT/f64_to_f32_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f64_to_f32 > $OUTPUT/f64_to_f32_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f64_to_f32 > $OUTPUT/f64_to_f32_rnm.tv
|
||||
echo "Creating f64_to_f128 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f64_to_f128 > $OUTPUT/f64_to_f128_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f64_to_f128 > $OUTPUT/f64_to_f128_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f64_to_f128 > $OUTPUT/f64_to_f128_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f64_to_f128 > $OUTPUT/f64_to_f128_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f64_to_f128 > $OUTPUT/f64_to_f128_rnm.tv
|
||||
echo "Creating f128_to_f16 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f128_to_f16 > $OUTPUT/f128_to_f16_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f128_to_f16 > $OUTPUT/f128_to_f16_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f128_to_f16 > $OUTPUT/f128_to_f16_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f128_to_f16 > $OUTPUT/f128_to_f16_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f128_to_f16 > $OUTPUT/f128_to_f16_rnm.tv
|
||||
echo "Creating f128_to_f32 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f128_to_f32 > $OUTPUT/f128_to_f32_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f128_to_f32 > $OUTPUT/f128_to_f32_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f128_to_f32 > $OUTPUT/f128_to_f32_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f128_to_f32 > $OUTPUT/f128_to_f32_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f128_to_f32 > $OUTPUT/f128_to_f32_rnm.tv
|
||||
echo "Creating f128_to_f64 convert vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f128_to_f64 > $OUTPUT/f128_to_f64_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f128_to_f64 > $OUTPUT/f128_to_f64_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f128_to_f64 > $OUTPUT/f128_to_f64_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f128_to_f64 > $OUTPUT/f128_to_f64_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f128_to_f64 > $OUTPUT/f128_to_f64_rnm.tv
|
||||
echo "Creating f16_add vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_add > $OUTPUT/f16_add_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_add > $OUTPUT/f16_add_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_add > $OUTPUT/f16_add_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_add > $OUTPUT/f16_add_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_add > $OUTPUT/f16_add_rnm.tv
|
||||
echo "Creating f32_add vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_add > $OUTPUT/f32_add_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_add > $OUTPUT/f32_add_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_add > $OUTPUT/f32_add_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_add > $OUTPUT/f32_add_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_add > $OUTPUT/f32_add_rnm.tv
|
||||
echo "Creating f64_add vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_add > $OUTPUT/f64_add_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_add > $OUTPUT/f64_add_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_add > $OUTPUT/f64_add_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_add > $OUTPUT/f64_add_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_add > $OUTPUT/f64_add_rnm.tv
|
||||
echo "Creating f128_add vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_add > $OUTPUT/f128_add_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_add > $OUTPUT/f128_add_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_add > $OUTPUT/f128_add_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_add > $OUTPUT/f128_add_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_add > $OUTPUT/f128_add_rnm.tv
|
||||
echo "Creating f16_sub vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_sub > $OUTPUT/f16_sub_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_sub > $OUTPUT/f16_sub_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_sub > $OUTPUT/f16_sub_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_sub > $OUTPUT/f16_sub_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_sub > $OUTPUT/f16_sub_rnm.tv
|
||||
echo "Creating f32_sub vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_sub > $OUTPUT/f32_sub_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_sub > $OUTPUT/f32_sub_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_sub > $OUTPUT/f32_sub_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_sub > $OUTPUT/f32_sub_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_sub > $OUTPUT/f32_sub_rnm.tv
|
||||
echo "Creating f64_sub vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_sub > $OUTPUT/f64_sub_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_sub > $OUTPUT/f64_sub_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_sub > $OUTPUT/f64_sub_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_sub > $OUTPUT/f64_sub_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_sub > $OUTPUT/f64_sub_rnm.tv
|
||||
echo "Creating f128_sub vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_sub > $OUTPUT/f128_sub_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_sub > $OUTPUT/f128_sub_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_sub > $OUTPUT/f128_sub_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_sub > $OUTPUT/f128_sub_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_sub > $OUTPUT/f128_sub_rnm.tv
|
||||
echo "Creating f16_mul vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_mul > $OUTPUT/f16_mul_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_mul > $OUTPUT/f16_mul_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_mul > $OUTPUT/f16_mul_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_mul > $OUTPUT/f16_mul_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_mul > $OUTPUT/f16_mul_rnm.tv
|
||||
echo "Creating f32_mul vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_mul > $OUTPUT/f32_mul_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_mul > $OUTPUT/f32_mul_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_mul > $OUTPUT/f32_mul_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_mul > $OUTPUT/f32_mul_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_mul > $OUTPUT/f32_mul_rnm.tv
|
||||
echo "Creating f64_mul vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_mul > $OUTPUT/f64_mul_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_mul > $OUTPUT/f64_mul_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_mul > $OUTPUT/f64_mul_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_mul > $OUTPUT/f64_mul_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_mul > $OUTPUT/f64_mul_rnm.tv
|
||||
echo "Creating f128_mul vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_mul > $OUTPUT/f128_mul_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_mul > $OUTPUT/f128_mul_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_mul > $OUTPUT/f128_mul_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_mul > $OUTPUT/f128_mul_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_mul > $OUTPUT/f128_mul_rnm.tv
|
||||
echo "Creating f16_div vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_div > $OUTPUT/f16_div_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_div > $OUTPUT/f16_div_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_div > $OUTPUT/f16_div_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_div > $OUTPUT/f16_div_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_div > $OUTPUT/f16_div_rnm.tv
|
||||
echo "Creating f32_div vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_div > $OUTPUT/f32_div_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_div > $OUTPUT/f32_div_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_div > $OUTPUT/f32_div_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_div > $OUTPUT/f32_div_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_div > $OUTPUT/f32_div_rnm.tv
|
||||
echo "Creating f64_div vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_div > $OUTPUT/f64_div_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_div > $OUTPUT/f64_div_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_div > $OUTPUT/f64_div_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_div > $OUTPUT/f64_div_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_div > $OUTPUT/f64_div_rnm.tv
|
||||
echo "Creating f128_div vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_div > $OUTPUT/f128_div_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_div > $OUTPUT/f128_div_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_div > $OUTPUT/f128_div_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_div > $OUTPUT/f128_div_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_div > $OUTPUT/f128_div_rnm.tv
|
||||
echo "Creating f16_sqrt vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f16_sqrt > $OUTPUT/f16_sqrt_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f16_sqrt > $OUTPUT/f16_sqrt_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f16_sqrt > $OUTPUT/f16_sqrt_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f16_sqrt > $OUTPUT/f16_sqrt_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f16_sqrt > $OUTPUT/f16_sqrt_rnm.tv
|
||||
echo "Creating f32_sqrt vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f32_sqrt > $OUTPUT/f32_sqrt_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f32_sqrt > $OUTPUT/f32_sqrt_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f32_sqrt > $OUTPUT/f32_sqrt_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f32_sqrt > $OUTPUT/f32_sqrt_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f32_sqrt > $OUTPUT/f32_sqrt_rnm.tv
|
||||
echo "Creating f64_sqrt vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f64_sqrt > $OUTPUT/f64_sqrt_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f64_sqrt > $OUTPUT/f64_sqrt_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f64_sqrt > $OUTPUT/f64_sqrt_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f64_sqrt > $OUTPUT/f64_sqrt_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f64_sqrt > $OUTPUT/f64_sqrt_rnm.tv
|
||||
echo "Creating f128_sqrt vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f128_sqrt > $OUTPUT/f128_sqrt_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f128_sqrt > $OUTPUT/f128_sqrt_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f128_sqrt > $OUTPUT/f128_sqrt_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f128_sqrt > $OUTPUT/f128_sqrt_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f128_sqrt > $OUTPUT/f128_sqrt_rnm.tv
|
||||
echo "Creating f16_eq vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_eq > $OUTPUT/f16_eq_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_eq > $OUTPUT/f16_eq_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_eq > $OUTPUT/f16_eq_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_eq > $OUTPUT/f16_eq_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_eq > $OUTPUT/f16_eq_rnm.tv
|
||||
echo "Creating f32_eq vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_eq > $OUTPUT/f32_eq_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_eq > $OUTPUT/f32_eq_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_eq > $OUTPUT/f32_eq_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_eq > $OUTPUT/f32_eq_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_eq > $OUTPUT/f32_eq_rnm.tv
|
||||
echo "Creating f64_eq vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_eq > $OUTPUT/f64_eq_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_eq > $OUTPUT/f64_eq_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_eq > $OUTPUT/f64_eq_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_eq > $OUTPUT/f64_eq_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_eq > $OUTPUT/f64_eq_rnm.tv
|
||||
echo "Creating f128_eq vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_eq > $OUTPUT/f128_eq_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_eq > $OUTPUT/f128_eq_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_eq > $OUTPUT/f128_eq_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_eq > $OUTPUT/f128_eq_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_eq > $OUTPUT/f128_eq_rnm.tv
|
||||
echo "Creating f16_le vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_le > $OUTPUT/f16_le_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_le > $OUTPUT/f16_le_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_le > $OUTPUT/f16_le_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_le > $OUTPUT/f16_le_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_le > $OUTPUT/f16_le_rnm.tv
|
||||
echo "Creating f32_le vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_le > $OUTPUT/f32_le_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_le > $OUTPUT/f32_le_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_le > $OUTPUT/f32_le_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_le > $OUTPUT/f32_le_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_le > $OUTPUT/f32_le_rnm.tv
|
||||
echo "Creating f64_le vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_le > $OUTPUT/f64_le_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_le > $OUTPUT/f64_le_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_le > $OUTPUT/f64_le_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_le > $OUTPUT/f64_le_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_le > $OUTPUT/f64_le_rnm.tv
|
||||
echo "Creating f128_le vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_le > $OUTPUT/f128_le_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_le > $OUTPUT/f128_le_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_le > $OUTPUT/f128_le_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_le > $OUTPUT/f128_le_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_le > $OUTPUT/f128_le_rnm.tv
|
||||
echo "Creating f16_lt vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_lt > $OUTPUT/f16_lt_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_lt > $OUTPUT/f16_lt_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_lt > $OUTPUT/f16_lt_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_lt > $OUTPUT/f16_lt_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_lt > $OUTPUT/f16_lt_rnm.tv
|
||||
echo "Creating f32_lt vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_lt > $OUTPUT/f32_lt_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_lt > $OUTPUT/f32_lt_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_lt > $OUTPUT/f32_lt_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_lt > $OUTPUT/f32_lt_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_lt > $OUTPUT/f32_lt_rnm.tv
|
||||
echo "Creating f64_lt vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_lt > $OUTPUT/f64_lt_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_lt > $OUTPUT/f64_lt_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_lt > $OUTPUT/f64_lt_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_lt > $OUTPUT/f64_lt_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_lt > $OUTPUT/f64_lt_rnm.tv
|
||||
echo "Creating f128_lt vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_lt > $OUTPUT/f128_lt_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_lt > $OUTPUT/f128_lt_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_lt > $OUTPUT/f128_lt_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_lt > $OUTPUT/f128_lt_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_lt > $OUTPUT/f128_lt_rnm.tv
|
||||
echo "Creating f16_mulAdd vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_mulAdd > $OUTPUT/f16_mulAdd_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_mulAdd > $OUTPUT/f16_mulAdd_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_mulAdd > $OUTPUT/f16_mulAdd_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_mulAdd > $OUTPUT/f16_mulAdd_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_mulAdd > $OUTPUT/f16_mulAdd_rnm.tv
|
||||
echo "Creating f32_mulAdd vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_mulAdd > $OUTPUT/f32_mulAdd_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_mulAdd > $OUTPUT/f32_mulAdd_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_mulAdd > $OUTPUT/f32_mulAdd_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_mulAdd > $OUTPUT/f32_mulAdd_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_mulAdd > $OUTPUT/f32_mulAdd_rnm.tv
|
||||
echo "Creating f64_mulAdd vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_mulAdd > $OUTPUT/f64_mulAdd_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_mulAdd > $OUTPUT/f64_mulAdd_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_mulAdd > $OUTPUT/f64_mulAdd_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_mulAdd > $OUTPUT/f64_mulAdd_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_mulAdd > $OUTPUT/f64_mulAdd_rnm.tv
|
||||
echo "Creating f128_mulAdd vectors"
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_mulAdd > $OUTPUT/f128_mulAdd_rne.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_mulAdd > $OUTPUT/f128_mulAdd_rz.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_mulAdd > $OUTPUT/f128_mulAdd_ru.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_mulAdd > $OUTPUT/f128_mulAdd_rd.tv
|
||||
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_mulAdd > $OUTPUT/f128_mulAdd_rnm.tv
|
||||
@ -1,483 +0,0 @@
|
||||
#!/bin/sh
|
||||
BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC"
|
||||
OUTPUT="./vectors"
|
||||
echo "Editing ui32_to_f16 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f16_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f16_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f16_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f16_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f16_rnm.tv
|
||||
echo "Editing ui32_to_f32 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f32_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f32_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f32_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f32_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f32_rnm.tv
|
||||
echo "Editing ui32_to_f64 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f64_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f64_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f64_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f64_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f64_rnm.tv
|
||||
echo "Editing ui32_to_f128 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f128_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f128_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f128_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f128_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui32_to_f128_rnm.tv
|
||||
echo "Editing ui64_to_f16 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f16_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f16_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f16_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f16_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f16_rnm.tv
|
||||
echo "Editing ui64_to_f32 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f32_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f32_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f32_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f32_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f32_rnm.tv
|
||||
echo "Editing ui64_to_f64 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f64_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f64_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f64_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f64_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f64_rnm.tv
|
||||
echo "Editing ui64_to_f128 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f128_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f128_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f128_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f128_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/ui64_to_f128_rnm.tv
|
||||
echo "Editing i32_to_f16 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f16_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f16_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f16_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f16_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f16_rnm.tv
|
||||
echo "Editing i32_to_f32 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f32_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f32_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f32_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f32_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f32_rnm.tv
|
||||
echo "Editing i32_to_f64 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f64_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f64_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f64_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f64_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f64_rnm.tv
|
||||
echo "Editing i32_to_f128 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f128_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f128_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f128_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f128_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i32_to_f128_rnm.tv
|
||||
echo "Editing i64_to_f16 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f16_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f16_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f16_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f16_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f16_rnm.tv
|
||||
echo "Editing i64_to_f32 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f32_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f32_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f32_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f32_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f32_rnm.tv
|
||||
echo "Editing i64_to_f64 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f64_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f64_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f64_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f64_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f64_rnm.tv
|
||||
echo "Editing i64_to_f128 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f128_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f128_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f128_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f128_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/i64_to_f128_rnm.tv
|
||||
echo "Editing f16_to_ui32 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_ui32_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_ui32_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_ui32_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_ui32_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_ui32_rnm.tv
|
||||
echo "Editing f32_to_ui32 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_ui32_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_ui32_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_ui32_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_ui32_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_ui32_rnm.tv
|
||||
echo "Editing f64_to_ui32 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_ui32_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_ui32_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_ui32_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_ui32_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_ui32_rnm.tv
|
||||
echo "Editing f128_to_ui32 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_ui32_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_ui32_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_ui32_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_ui32_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_ui32_rnm.tv
|
||||
echo "Editing f16_to_ui64 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_ui64_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_ui64_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_ui64_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_ui64_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_ui64_rnm.tv
|
||||
echo "Editing f32_to_ui64 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_ui64_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_ui64_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_ui64_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_ui64_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_ui64_rnm.tv
|
||||
echo "Editing f64_to_ui64 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_ui64_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_ui64_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_ui64_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_ui64_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_ui64_rnm.tv
|
||||
echo "Editing f128_to_ui64 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_ui64_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_ui64_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_ui64_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_ui64_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_ui64_rnm.tv
|
||||
echo "Editing f16_to_i32 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_i32_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_i32_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_i32_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_i32_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_i32_rnm.tv
|
||||
echo "Editing f32_to_i32 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_i32_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_i32_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_i32_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_i32_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_i32_rnm.tv
|
||||
echo "Editing f64_to_i32 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_i32_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_i32_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_i32_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_i32_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_i32_rnm.tv
|
||||
echo "Editing f128_to_i32 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_i32_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_i32_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_i32_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_i32_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_i32_rnm.tv
|
||||
echo "Editing f16_to_i64 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_i64_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_i64_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_i64_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_i64_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_i64_rnm.tv
|
||||
echo "Editing f32_to_i64 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_i64_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_i64_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_i64_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_i64_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_i64_rnm.tv
|
||||
echo "Editing f64_to_i64 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_i64_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_i64_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_i64_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_i64_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_i64_rnm.tv
|
||||
echo "Editing f128_to_i64 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_i64_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_i64_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_i64_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_i64_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_i64_rnm.tv
|
||||
echo "Editing f16_to_f32 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_f32_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_f32_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_f32_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_f32_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_f32_rnm.tv
|
||||
echo "Editing f16_to_f64 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_f64_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_f64_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_f64_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_f64_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_f64_rnm.tv
|
||||
echo "Editing f16_to_f128 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_f128_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_f128_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_f128_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_f128_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_to_f128_rnm.tv
|
||||
echo "Editing f32_to_f16 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_f16_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_f16_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_f16_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_f16_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_f16_rnm.tv
|
||||
echo "Editing f32_to_f64 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_f64_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_f64_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_f64_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_f64_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_f64_rnm.tv
|
||||
echo "Editing f32_to_f128 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_f128_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_f128_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_f128_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_f128_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_to_f128_rnm.tv
|
||||
echo "Editing f64_to_f16 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_f16_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_f16_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_f16_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_f16_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_f16_rnm.tv
|
||||
echo "Editing f64_to_f32 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_f32_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_f32_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_f32_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_f32_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_f32_rnm.tv
|
||||
echo "Editing f64_to_f128 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_f128_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_f128_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_f128_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_f128_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_to_f128_rnm.tv
|
||||
echo "Editing f128_to_f16 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_f16_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_f16_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_f16_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_f16_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_f16_rnm.tv
|
||||
echo "Editing f128_to_f32 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_f32_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_f32_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_f32_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_f32_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_f32_rnm.tv
|
||||
echo "Editing f128_to_f64 test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_f64_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_f64_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_f64_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_f64_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_to_f64_rnm.tv
|
||||
echo "Editing f16_add test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_add_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_add_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_add_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_add_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_add_rnm.tv
|
||||
echo "Editing f32_add test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_add_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_add_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_add_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_add_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_add_rnm.tv
|
||||
echo "Editing f64_add test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_add_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_add_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_add_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_add_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_add_rnm.tv
|
||||
echo "Editing f128_add test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_add_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_add_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_add_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_add_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_add_rnm.tv
|
||||
echo "Editing f16_sub test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_sub_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_sub_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_sub_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_sub_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_sub_rnm.tv
|
||||
echo "Editing f32_sub test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_sub_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_sub_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_sub_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_sub_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_sub_rnm.tv
|
||||
echo "Editing f64_sub test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_sub_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_sub_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_sub_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_sub_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_sub_rnm.tv
|
||||
echo "Editing f128_sub test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_sub_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_sub_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_sub_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_sub_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_sub_rnm.tv
|
||||
echo "Editing f16_mul test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_mul_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_mul_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_mul_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_mul_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_mul_rnm.tv
|
||||
echo "Editing f32_mul test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_mul_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_mul_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_mul_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_mul_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_mul_rnm.tv
|
||||
echo "Editing f64_mul test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_mul_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_mul_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_mul_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_mul_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_mul_rnm.tv
|
||||
echo "Editing f128_mul test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_mul_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_mul_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_mul_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_mul_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_mul_rnm.tv
|
||||
echo "Editing f16_div test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_div_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_div_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_div_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_div_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_div_rnm.tv
|
||||
echo "Editing f32_div test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_div_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_div_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_div_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_div_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_div_rnm.tv
|
||||
echo "Editing f64_div test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_div_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_div_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_div_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_div_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_div_rnm.tv
|
||||
echo "Editing f128_div test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_div_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_div_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_div_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_div_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_div_rnm.tv
|
||||
echo "Editing f16_sqrt test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_sqrt_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_sqrt_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_sqrt_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_sqrt_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_sqrt_rnm.tv
|
||||
echo "Editing f32_sqrt test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_sqrt_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_sqrt_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_sqrt_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_sqrt_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_sqrt_rnm.tv
|
||||
echo "Editing f64_sqrt test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_sqrt_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_sqrt_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_sqrt_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_sqrt_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_sqrt_rnm.tv
|
||||
echo "Editing f128_sqrt test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_sqrt_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_sqrt_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_sqrt_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_sqrt_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_sqrt_rnm.tv
|
||||
echo "Editing f16_eq test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_eq_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_eq_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_eq_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_eq_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_eq_rnm.tv
|
||||
echo "Editing f32_eq test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_eq_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_eq_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_eq_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_eq_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_eq_rnm.tv
|
||||
echo "Editing f64_eq test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_eq_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_eq_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_eq_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_eq_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_eq_rnm.tv
|
||||
echo "Editing f128_eq test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_eq_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_eq_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_eq_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_eq_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_eq_rnm.tv
|
||||
echo "Editing f16_le test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_le_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_le_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_le_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_le_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_le_rnm.tv
|
||||
echo "Editing f32_le test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_le_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_le_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_le_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_le_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_le_rnm.tv
|
||||
echo "Editing f64_le test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_le_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_le_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_le_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_le_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_le_rnm.tv
|
||||
echo "Editing f128_le test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_le_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_le_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_le_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_le_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_le_rnm.tv
|
||||
echo "Editing f16_lt test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_lt_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_lt_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_lt_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_lt_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_lt_rnm.tv
|
||||
echo "Editing f32_lt test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_lt_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_lt_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_lt_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_lt_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_lt_rnm.tv
|
||||
echo "Editing f64_lt test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_lt_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_lt_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_lt_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_lt_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_lt_rnm.tv
|
||||
echo "Editing f128_lt test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_lt_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_lt_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_lt_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_lt_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_lt_rnm.tv
|
||||
echo "Editing f16_mulAdd test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rnm.tv
|
||||
echo "Editing f32_mulAdd test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rnm.tv
|
||||
echo "Editing f64_mulAdd test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rnm.tv
|
||||
echo "Editing f128_mulAdd test vectors"
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rne.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rz.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_ru.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rd.tv
|
||||
sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rnm.tv
|
||||
81
tests/fp/vectors/Makefile
Executable file
81
tests/fp/vectors/Makefile
Executable file
@ -0,0 +1,81 @@
|
||||
.DELETE_ON_ERROR:
|
||||
SHELL := /bin/bash
|
||||
|
||||
TESTFLOAT_DIR := ${WALLY}/addins/TestFloat-3e/build/Linux-x86_64-GCC
|
||||
TESTFLOAT_GEN_CMD := ${TESTFLOAT_DIR}/testfloat_gen -tininessafter -level
|
||||
|
||||
# List of testvectors to generate. Each rounding mode will be generated for each test.
|
||||
convert := ui32_to_f16 ui32_to_f32 ui32_to_f64 ui32_to_f128 \
|
||||
ui64_to_f16 ui64_to_f32 ui64_to_f64 ui64_to_f128 \
|
||||
i32_to_f16 i32_to_f32 i32_to_f64 i32_to_f128 \
|
||||
i64_to_f16 i64_to_f32 i64_to_f64 i64_to_f128 \
|
||||
f16_to_ui32 f32_to_ui32 f64_to_ui32 f128_to_ui32 \
|
||||
f16_to_ui64 f32_to_ui64 f64_to_ui64 f128_to_ui64 \
|
||||
f16_to_i32 f32_to_i32 f64_to_i32 f128_to_i32 \
|
||||
f16_to_i64 f32_to_i64 f64_to_i64 f128_to_i64 \
|
||||
f16_to_f32 f16_to_f64 f16_to_f128 \
|
||||
f32_to_f16 f32_to_f64 f32_to_f128 \
|
||||
f64_to_f16 f64_to_f32 f64_to_f128 \
|
||||
f128_to_f16 f128_to_f32 f128_to_f64
|
||||
add := f16_add f32_add f64_add f128_add
|
||||
sub := f16_sub f32_sub f64_sub f128_sub
|
||||
mul := f16_mul f32_mul f64_mul f128_mul
|
||||
div := f16_div f32_div f64_div f128_div
|
||||
sqrt := f16_sqrt f32_sqrt f64_sqrt f128_sqrt
|
||||
eq := f16_eq f32_eq f64_eq f128_eq
|
||||
le := f16_le f32_le f64_le f128_le
|
||||
lt := f16_lt f32_lt f64_lt f128_lt
|
||||
mulAdd := f16_mulAdd f32_mulAdd f64_mulAdd f128_mulAdd
|
||||
|
||||
tests := $(convert) $(add) $(sub) $(mul) $(div) $(sqrt) $(eq) $(le) $(lt) $(mulAdd)
|
||||
|
||||
|
||||
.PHONY: all rne rz ru rd rnm clean
|
||||
|
||||
all: rne rz ru rd rnm
|
||||
|
||||
# Generate test vectors for each rounding mode
|
||||
rne: $(addsuffix _rne.tv, $(tests))
|
||||
rz: $(addsuffix _rz.tv, $(tests))
|
||||
ru: $(addsuffix _ru.tv, $(tests))
|
||||
rd: $(addsuffix _rd.tv, $(tests))
|
||||
rnm: $(addsuffix _rnm.tv, $(tests))
|
||||
|
||||
# Rules to generate individual test vectors, broken up by rounding mode
|
||||
%_rne.tv: ${TESTFLOAT_GEN}
|
||||
@echo Creating $*_rne.tv vectors
|
||||
@if [[ "$*" =~ "to" ]] || [[ "$*" =~ "sqrt" ]] ; then level=2 ; else level=1 ; fi ; \
|
||||
${TESTFLOAT_GEN_CMD} $$level -rnear_even $* > $@
|
||||
@sed -i 's/ /_/g' $@
|
||||
|
||||
%_rz.tv: ${TESTFLOAT_GEN}
|
||||
@echo Creating $*_rz.tv vectors
|
||||
@if [[ "$*" =~ "to" ]] || [[ "$*" =~ "sqrt" ]] ; then level=2 ; else level=1 ; fi ; \
|
||||
${TESTFLOAT_GEN_CMD} $$level -rminMag $* > $@
|
||||
@sed -i 's/ /_/g' $@
|
||||
|
||||
%_ru.tv: ${TESTFLOAT_GEN}
|
||||
@echo Creating $*_ru.tv vectors
|
||||
@if [[ "$*" =~ "to" ]] || [[ "$*" =~ "sqrt" ]] ; then level=2 ; else level=1 ; fi ; \
|
||||
${TESTFLOAT_GEN_CMD} $$level -rmax $* > $@
|
||||
@sed -i 's/ /_/g' $@
|
||||
|
||||
%_rd.tv: ${TESTFLOAT_GEN}
|
||||
@echo Creating $*_rd.tv vectors
|
||||
@if [[ "$*" =~ "to" ]] || [[ "$*" =~ "sqrt" ]] ; then level=2 ; else level=1 ; fi ; \
|
||||
${TESTFLOAT_GEN_CMD} $$level -rmin $* > $@
|
||||
@sed -i 's/ /_/g' $@
|
||||
|
||||
%_rnm.tv: ${TESTFLOAT_GEN}
|
||||
@echo Creating $*_rnm.tv vectors
|
||||
@if [[ "$*" =~ "to" ]] || [[ "$*" =~ "sqrt" ]] ; then level=2 ; else level=1 ; fi ; \
|
||||
${TESTFLOAT_GEN_CMD} $$level -rnear_maxMag $* > $@
|
||||
@sed -i 's/ /_/g' $@
|
||||
|
||||
# Generate TestFloat first if necessary
|
||||
${TESTFLOAT_GEN}:
|
||||
$(MAKE) -C ${WALLY}/tests/fp testfloat
|
||||
|
||||
clean:
|
||||
rm -f *.tv
|
||||
rm -f sed*
|
||||
@ -6,6 +6,7 @@ arch_workdir = $(work)/riscv-arch-test
|
||||
wally_workdir = $(work)/wally-riscv-arch-test
|
||||
custom_test_dir = ../../addins/cvw-arch-verif/test
|
||||
submodule_work_dir = ../../addins/cvw-arch-verif/riscof_work
|
||||
nproc = $(shell nproc --ignore=1)
|
||||
|
||||
current_dir = $(shell pwd)
|
||||
#XLEN ?= 64
|
||||
@ -21,9 +22,9 @@ root:
|
||||
mkdir -p $(work)
|
||||
mkdir -p $(arch_workdir)
|
||||
mkdir -p $(wally_workdir)
|
||||
sed 's,{0},$(current_dir),g;s,{1},32gc,g' config.ini > config32.ini
|
||||
sed 's,{0},$(current_dir),g;s,{1},64gc,g' config.ini > config64.ini
|
||||
sed 's,{0},$(current_dir),g;s,{1},32e,g' config.ini > config32e.ini
|
||||
sed 's,{0},$(current_dir),g;s,{1},32gc,g;s,{2},$(nproc),g' config.ini > config32.ini
|
||||
sed 's,{0},$(current_dir),g;s,{1},64gc,g;s,{2},$(nproc),g' config.ini > config64.ini
|
||||
sed 's,{0},$(current_dir),g;s,{1},32e,g;s,{2},$(nproc),g' config.ini > config32e.ini
|
||||
|
||||
arch32e:
|
||||
riscof run --work-dir=$(work_dir) --config=config32e.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser
|
||||
|
||||
@ -10,8 +10,8 @@ ispec={0}/spike/spike_rv{1}_isa.yaml
|
||||
pspec={0}/spike/spike_platform.yaml
|
||||
target_run=1
|
||||
# Optional as mentioned in https://riscof.readthedocs.io/en/latest/inputs.html#config-ini-syntax
|
||||
jobs=4
|
||||
jobs={2}
|
||||
|
||||
[sail_cSim]
|
||||
pluginpath={0}/sail_cSim
|
||||
jobs=4
|
||||
jobs={2}
|
||||
|
||||
@ -55,7 +55,7 @@ def toint(x: str):
|
||||
return int(x)
|
||||
|
||||
def get_rm(opcode):
|
||||
insns = ['fsgnj','fle','flt','feq','fclass','fmv','flw','fsw','fld','fsd','fmin','fmax',
|
||||
insns = ['fsgnj','fle','flt','feq','fclass','fmv','flw','fsw','fld','fsd','flq','fsq','fmin','fmax',
|
||||
'fcvt.d.s', 'fcvt.d.w','fcvt.d.wu']
|
||||
insns += ['fminm', 'fmaxm']
|
||||
if any([x in opcode for x in insns]):
|
||||
@ -242,7 +242,7 @@ class Generator():
|
||||
|
||||
|
||||
is_nan_box = False
|
||||
is_fext = any(['F' in x or 'D' in x for x in opnode['isa']])
|
||||
is_fext = any(['F' in x or 'D' in x or 'Q' in x for x in opnode['isa']])
|
||||
|
||||
if is_fext:
|
||||
if fl>ifl:
|
||||
@ -260,7 +260,7 @@ class Generator():
|
||||
self.is_fext = is_fext
|
||||
self.is_nan_box = is_nan_box
|
||||
|
||||
if opcode in ['sw', 'sh', 'sb', 'lw', 'lhu', 'lh', 'lb', 'lbu', 'ld', 'lwu', 'sd',"jal","beq","bge","bgeu","blt","bltu","bne","jalr","flw","fsw","fld","fsd"]:
|
||||
if opcode in ['sw', 'sh', 'sb', 'lw', 'lhu', 'lh', 'lb', 'lbu', 'ld', 'lwu', 'sd',"jal","beq","bge","bgeu","blt","bltu","bne","jalr","flw","fsw","fld","fsd","flq","fsq"]:
|
||||
self.val_vars = self.val_vars + ['ea_align']
|
||||
self.template = opnode['template']
|
||||
self.opnode = opnode
|
||||
|
||||
@ -2,7 +2,7 @@ import struct
|
||||
|
||||
instrs_sig_mutable = ['auipc','jal','jalr']
|
||||
instrs_sig_update = ['sh','sb','sw','sd','c.sw','c.sd','c.swsp','c.sdsp','fsw','fsd',\
|
||||
'c.fsw','c.fsd','c.fswsp','c.fsdsp']
|
||||
'fsq','c.fsw','c.fsd','c.fswsp','c.fsdsp']
|
||||
instrs_no_reg_tracking = ['beq','bne','blt','bge','bltu','bgeu','fence','c.j','c.jal','c.jalr',\
|
||||
'c.jr','c.beqz','c.bnez', 'c.ebreak'] + instrs_sig_update
|
||||
instrs_fcsr_affected = ['fmadd.s','fmsub.s','fnmsub.s','fnmadd.s','fadd.s','fsub.s','fmul.s','fdiv.s',\
|
||||
@ -11,8 +11,8 @@ instrs_fcsr_affected = ['fmadd.s','fmsub.s','fnmsub.s','fnmadd.s','fadd.s','fsub
|
||||
'fcvt.s.lu', 'fmadd.d','fmsub.d','fnmsub.d','fnmadd.d','fadd.d','fsub.d',\
|
||||
'fmul.d','fdiv.d','fsqrt.d','fmin.d','fmax.d','fcvt.s.d','fcvt.d.s',\
|
||||
'feq.d','flt.d','fle.d','fcvt.w.d','fcvt.wu.d','fcvt.l.d','fcvt.lu.d',\
|
||||
'fcvt.d.l','fcvt.d.lu']
|
||||
unsgn_rs1 = ['sw','sd','sh','sb','ld','lw','lwu','lh','lhu','lb', 'lbu','flw','fld','fsw','fsd',\
|
||||
'fcvt.d.l','fcvt.d.lu','fadd.q','fsub.q','fmadd.q','fmsub.q','fnmsub.q','fnmadd.q']
|
||||
unsgn_rs1 = ['sw','sd','sh','sb','ld','lw','lwu','lh','lhu','lb', 'lbu','flw','fld','flq','fsw','fsd','fsq',\
|
||||
'bgeu', 'bltu', 'sltiu', 'sltu','c.lw','c.ld','c.lwsp','c.ldsp',\
|
||||
'c.sw','c.sd','c.swsp','c.sdsp','mulhu','divu','remu','divuw',\
|
||||
'remuw','aes64ds','aes64dsm','aes64es','aes64esm','aes64ks2',\
|
||||
@ -33,9 +33,9 @@ unsgn_rs2 = ['bgeu', 'bltu', 'sltiu', 'sltu', 'sll', 'srl', 'sra','mulhu',\
|
||||
'xperm.n','xperm.b', 'aes32esmi', 'aes32esi', 'aes32dsmi', 'aes32dsi',\
|
||||
'sha512sum1r','sha512sum0r','sha512sig1l','sha512sig1h','sha512sig0l','sha512sig0h','fsw',\
|
||||
'bclr','bext','binv','bset','minu','maxu','add.uw','sh1add.uw','sh2add.uw','sh3add.uw']
|
||||
f_instrs_pref = ['fadd', 'fclass', 'fcvt', 'fdiv', 'feq', 'fld', 'fle', 'flt', 'flw', 'fmadd',\
|
||||
f_instrs_pref = ['fadd', 'fclass', 'fcvt', 'fdiv', 'feq', 'fld','flq', 'fle', 'flt', 'flw', 'fmadd',\
|
||||
'fmax', 'fmin', 'fmsub', 'fmul', 'fmv', 'fnmadd', 'fnmsub', 'fsd', 'fsgnj', 'fsqrt',\
|
||||
'fsub', 'fsw']
|
||||
'fsub', 'fsw','fsq']
|
||||
|
||||
|
||||
instr_var_evaluator_funcs = {} # dictionary for holding registered evaluator funcs
|
||||
@ -146,6 +146,8 @@ class instructionObject():
|
||||
instr_vars['iflen'] = 32
|
||||
elif self.instr_name.endswith(".d"):
|
||||
instr_vars['iflen'] = 64
|
||||
elif self.instr_name.endswith(".q"):
|
||||
instr_vars['iflen'] = 128
|
||||
|
||||
# capture the operands
|
||||
if self.rs1 is not None:
|
||||
@ -179,6 +181,8 @@ class instructionObject():
|
||||
ea_align = (rs1_val + imm_val) % 4
|
||||
if self.instr_name in ['ld','sd','fld','fsd']:
|
||||
ea_align = (rs1_val + imm_val) % 8
|
||||
if self.instr_name in ['flq','fsq']:
|
||||
ea_align = (rs1_val + imm_val) % 16
|
||||
|
||||
instr_vars.update({
|
||||
'rs1_val': rs1_val,
|
||||
@ -439,9 +443,12 @@ class instructionObject():
|
||||
if iflen == 32:
|
||||
e_sz = 8
|
||||
m_sz = 23
|
||||
else:
|
||||
elif iflen == 64:
|
||||
e_sz = 11
|
||||
m_sz = 52
|
||||
elif iflen == 128:
|
||||
e_sz = 15
|
||||
m_sz = 112
|
||||
bin_val = ('{:0'+str(flen)+'b}').format(reg_val)
|
||||
|
||||
if flen > iflen:
|
||||
|
||||
@ -43,7 +43,7 @@ def simd_val_comb(xlen, bit_width, signed=True):
|
||||
:type signed: bool
|
||||
'''
|
||||
|
||||
fmt = {8: 'b', 16: 'h', 32: 'w', 64: 'd'}
|
||||
fmt = {8: 'b', 16: 'h', 32: 'w', 64: 'd', 128: 'q'}
|
||||
sz = fmt[bit_width]
|
||||
var_num = xlen//bit_width
|
||||
coverpoints = []
|
||||
@ -78,7 +78,7 @@ def simd_base_val(rs, xlen, bit_width, signed=True):
|
||||
:type signed: bool
|
||||
'''
|
||||
|
||||
fmt = {8: 'b', 16: 'h', 32: 'w', 64: 'd'}
|
||||
fmt = {8: 'b', 16: 'h', 32: 'w', 64: 'd', 128: 'q'}
|
||||
|
||||
sz = fmt[bit_width]
|
||||
var_num = xlen//bit_width
|
||||
|
||||
@ -536,8 +536,10 @@ class archState:
|
||||
|
||||
if flen == 32:
|
||||
self.f_rf = ['00000000']*32
|
||||
else:
|
||||
elif flen == 64:
|
||||
self.f_rf = ['0000000000000000']*32
|
||||
else:
|
||||
self.f_rf = ['00000000000000000000000000000']*32
|
||||
self.pc = 0
|
||||
self.flen = flen
|
||||
|
||||
|
||||
@ -362,7 +362,7 @@ class disassembler():
|
||||
if 'rs1' in arg:
|
||||
treg = reg_type
|
||||
if any([instr_name.startswith(x) for x in [
|
||||
'fsw','fsd','fcvt.s','fcvt.d','fmv.w','fmv.l']]):
|
||||
'fsw','fsd','fsq','fcvt.s','fcvt.d','fmv.w','fmv.l']]):
|
||||
treg = 'x'
|
||||
temp_instrobj.rs1 = (int(get_arg_val(arg)(mcode), 2), treg)
|
||||
if 'rs2' in arg:
|
||||
|
||||
@ -18,8 +18,8 @@ class disassembler():
|
||||
0b0011011: self.rv64i_arithi_ops,
|
||||
0b0111011: self.rv64i_arith_ops,
|
||||
0b0101111: self.rv64_rv32_atomic_ops,
|
||||
0b0000111: self.flw_fld,
|
||||
0b0100111: self.fsw_fsd,
|
||||
0b0000111: self.flw_fld_flq,
|
||||
0b0100111: self.fsw_fsd_fsq,
|
||||
0b1000011: self.fmadd,
|
||||
0b1000111: self.fmsub,
|
||||
0b1001011: self.fnmsub,
|
||||
@ -1606,7 +1606,7 @@ class disassembler():
|
||||
|
||||
return instrObj
|
||||
|
||||
def flw_fld(self, instrObj):
|
||||
def flw_fld_flq(self, instrObj):
|
||||
instr = instrObj.instr
|
||||
rd = ((instr & self.RD_MASK) >> 7, 'f')
|
||||
rs1 = ((instr & self.RS1_MASK) >> 15, 'x')
|
||||
@ -1621,10 +1621,12 @@ class disassembler():
|
||||
instrObj.instr_name = 'flw'
|
||||
elif funct3 == 0b011:
|
||||
instrObj.instr_name = 'fld'
|
||||
elif funct3 == 0b100:
|
||||
instrObj.instr_name = 'flq'
|
||||
|
||||
return instrObj
|
||||
|
||||
def fsw_fsd(self, instrObj):
|
||||
def fsw_fsd_fsq(self, instrObj):
|
||||
instr = instrObj.instr
|
||||
imm_4_0 = (instr & self.RD_MASK) >> 7
|
||||
imm_11_5 = (instr >> 25) << 5
|
||||
@ -1642,6 +1644,8 @@ class disassembler():
|
||||
instrObj.instr_name = 'fsw'
|
||||
elif funct3 == 0b011:
|
||||
instrObj.instr_name = 'fsd'
|
||||
elif funct3 == 0b100:
|
||||
instrObj.instr_name = 'fsq'
|
||||
|
||||
return instrObj
|
||||
|
||||
@ -1766,6 +1770,14 @@ class disassembler():
|
||||
instrObj.instr_name = 'fmul.d'
|
||||
elif funct7 == 0b0001101:
|
||||
instrObj.instr_name = 'fdiv.d'
|
||||
elif funct7 == 0b0000011:
|
||||
instrObj.instr_name = 'fadd.q'
|
||||
elif funct7 == 0b0000111:
|
||||
instrObj.instr_name = 'fsub.q'
|
||||
elif funct7 == 0b0001011:
|
||||
instrObj.instr_name = 'fmul.q'
|
||||
elif funct7 == 0b0001111:
|
||||
instrObj.instr_name = 'fdiv.q'
|
||||
|
||||
# fsqrt
|
||||
if funct7 == 0b0101100:
|
||||
@ -1776,6 +1788,10 @@ class disassembler():
|
||||
instrObj.instr_name = 'fsqrt.d'
|
||||
instrObj.rs2 = None
|
||||
return instrObj
|
||||
elif funct7 == 0b0101111:
|
||||
instrObj.instr_name = 'fsqrt.q'
|
||||
instrObj.rs2 = None
|
||||
return instrObj
|
||||
|
||||
# fsgnj, fsgnjn, fsgnjx
|
||||
if funct7 == 0b0010000:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user