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860 Commits

Author SHA1 Message Date
DTowersM
5e87506772 working makefile for embench and removed testbench-f64 2022-05-26 00:08:18 +00:00
slmnemo
17dff315f4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-25 17:03:26 -07:00
slmnemo
d43d340e31 added logic to prevent cache line length from exceeding the max size of a burst. 2022-05-25 17:03:15 -07:00
cturek
366cd5f1d5 Renamed variables for readability 2022-05-26 00:01:51 +00:00
cturek
650779318d Fixed exponent verification, added sign module and added sign tests 2022-05-25 23:36:21 +00:00
Katherine Parry
c264585fe8 single and double conversions pass all tests 2022-05-25 23:02:02 +00:00
Madeleine Masser-Frye
c8892f2847 ppaAnalyze: docstrings and tsmc28 plotting 2022-05-25 13:52:20 +00:00
Madeleine Masser-Frye
7d1448d2ad added support for tsmc28, fixed ff modules/analysis for timing 2022-05-25 06:44:22 +00:00
slmnemo
cd9f0cd6bd fixed a comment spelling typo 2022-05-23 19:24:28 -07:00
Katherine Parry
18bdaf0179 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-23 23:11:41 +00:00
Katherine Parry
37e74648a9 added exponents to srt divider 2022-05-23 23:07:27 +00:00
David Harris
2d175e2a37 Checked in qst2.c from James 2022-05-23 20:26:05 +00:00
Ross Thompson
1dde9db2ce Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-22 23:54:33 -05:00
Ross Thompson
13f7f48776 Possible plic fix? 2022-05-22 23:47:01 -05:00
Madeleine Masser-Frye
99aa110615 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-22 23:23:39 +00:00
Madeleine Masser-Frye
378523087f added widths for csa in ppa 2022-05-22 23:23:02 +00:00
Ross Thompson
ff8e158ec4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-22 10:55:33 -05:00
Ross Thompson
848abf29b5 Fixed receive fifo ITNR bug. 2022-05-22 10:55:28 -05:00
Ross Thompson
1318f702cf Added more debug signals to uart. 2022-05-21 19:47:40 -05:00
Madeleine Masser-Frye
0bcae85792 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-05-21 09:53:31 +00:00
Madeleine Masser-Frye
fcaf032a0d ppa updates 
added widths to modules, automated frequency sweep synthesis, added slack violation color coding to plots
 2022-05-21 09:53:26 +00:00
slmnemo
a5d5bd272b changes suggested by ben, hopefully fixing buildroot (which is now not running) 2022-05-20 18:42:38 -07:00
Katherine Parry
6bc31f2e78 Fixed unpacker bug LT EQ LE pass testfloat 2022-05-20 17:19:50 +00:00
slmnemo
af675bbefb Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-19 18:31:56 -07:00
slmnemo
4a2538455d added documentation for ahblite burst types to ahblite.sv 2022-05-19 18:31:46 -07:00
slmnemo
3b4286ec33 fixed lint autofailing due to no log being produced in regression-wally 2022-05-19 18:30:59 -07:00
slmnemo
6c237e43d8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-19 17:51:45 -07:00
slmnemo
a5490c7096 Added parameters for DEBUG_TRACE to buildroot, buildroot-checkpoint, and buildroot-notrace 2022-05-19 17:51:26 -07:00
slmnemo
05d14bdb3c Added parameter to keep tracking on for buildroot and buildroot-checkpoint in regression.py 2022-05-19 17:50:48 -07:00
slmnemo
0982417054 Fixed buildroot by adding a second . 2022-05-19 17:49:32 -07:00
slmnemo
7d2bfb6db8 parametrized linux testbench's DEBUG_TRACE and added parameters to relevant calls of the linux testbench in wally-pipelined.do 2022-05-19 16:21:38 -07:00
Katherine Parry
bc4804d90a fixed lint warning 2022-05-19 20:34:06 +00:00
Katherine Parry
b0881495a9 Bug fixed in unpacker and sub/add/mul tests pass TestFloat 2022-05-19 20:31:23 +00:00
mmasserfrye
b255f61521 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-19 20:24:57 +00:00
mmasserfrye
710905b239 updated synth plotting and regression 2022-05-19 20:24:47 +00:00
Katherine Parry
cc0ab94ebc Added fp tests - doesnpass yet 2022-05-19 16:32:30 +00:00
slmnemo
af14c8a064 added instructions to slack notifier 2022-05-18 16:50:31 -07:00
mmasserfrye
1442afe4e2 added support for plotting and fitting power 2022-05-18 17:01:55 +00:00
mmasserfrye
1888a9a665 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-18 16:10:36 +00:00
mmasserfrye
0265d1988e adapted shifter in ppa.sv for widths beside 32 and 64 
modified plotting and regression in ppaAnalyze.py
 2022-05-18 16:08:40 +00:00
Ross Thompson
9079e67aae Updated fpga debugger. 2022-05-17 23:04:01 -05:00
slmnemo
7cd673fa6e simplified make-tests.sh to run the current makefile in regression 2022-05-17 17:29:34 -07:00
slmnemo
ebeebf3bfc Revert "same as last breaking commit, testing if the bisect works to output a breaking commit." 
This reverts commit 910475ea56.

gottem
 2022-05-17 17:26:33 -07:00
slmnemo
910475ea56 same as last breaking commit, testing if the bisect works to output a breaking commit. 2022-05-17 17:22:09 -07:00
slmnemo
36ea0f9126 Revert "broke it again but this time it doesn't compile due to a missing semicolon on Rs1D." 
This reverts commit 0dea11fc73.

fixed it
 2022-05-17 17:05:11 -07:00
slmnemo
0dea11fc73 broke it again but this time it doesn't compile due to a missing semicolon on Rs1D. 2022-05-17 17:03:16 -07:00
slmnemo
73d19b0956 Revert "Intentionally broke wally by setting datapath Rs1D to use bits 18:14 instead of 19:15 to test regression" 
This reverts commit 83e4ab711c.

unbroke wally
 2022-05-17 16:57:29 -07:00
slmnemo
29bc8d6902 Revert "Revert "Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main"" 
This reverts commit c15aab9c6f.

reverted the wrong commit
 2022-05-17 16:57:00 -07:00
slmnemo
c15aab9c6f Revert "Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main" 
This reverts commit d601c89d2a, reversing
changes made to 1131d41343.

undid things
 2022-05-17 16:54:29 -07:00
slmnemo
83e4ab711c Intentionally broke wally by setting datapath Rs1D to use bits 18:14 instead of 19:15 to test regression 2022-05-17 16:33:09 -07:00
slmnemo
d601c89d2a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Added empty directory '/wkdir' to /pipelined/regression to avoid tests failing out of box due to the missing directory
 2022-05-17 20:32:53 +00:00
slmnemo
1131d41343 added wkdir in regression so regression runs out of box (assuming the old version of arch tests) 2022-05-17 20:32:38 +00:00
David Harris
83494e349b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-17 15:09:52 +00:00
David Harris
20c861ee6f Restored srt to working without exponent unit 2022-05-17 15:09:48 +00:00
mmasserfrye
43cf4f35cd Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-17 01:11:58 +00:00
mmasserfrye
24420dea6c added 8 and 128 bit versions, adjusted alu 2022-05-17 01:11:43 +00:00
slmnemo
ba572b46f4 Updated testbench to initialize using force and releases storing zero in all memory locations in branch predictor. Fixed arch64i bug related to failing bge due to an incorrect signature. 2022-05-17 01:04:13 +00:00
slmnemo
ede0a3237d quit 2022-05-17 01:03:09 +00:00
David Harris
0fb6fe4cc1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-17 00:07:09 +00:00
David Harris
b992a61ca3 removed exptestgen 2022-05-17 00:06:44 +00:00
David Harris
7aba83a35c Cleaned up unpacker changes in srt and lint errors 2022-05-17 00:06:14 +00:00
slmnemo
c84731d6d0 Fixed grammar on two comments in bpred.sv 2022-05-16 22:41:18 +00:00
mmasserfrye
c8e43e9798 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 
resolved merge conflict
 2022-05-16 15:42:59 +00:00
mmasserfrye
2ca897620f tuning modules for ppa 2022-05-16 15:39:15 +00:00
David Harris
f5e2cff45a Cause simplification 2022-05-12 23:47:21 +00:00
David Harris
6303d4e81f Cause simplification 2022-05-12 23:39:10 +00:00
David Harris
c4621c5b6b Cause simplification 2022-05-12 23:37:40 +00:00
David Harris
7daf631c13 Cause simplification 2022-05-12 23:33:35 +00:00
David Harris
de51c7eeb3 Cause simplification 2022-05-12 23:33:22 +00:00
David Harris
803bfc4fe4 Cause simplification 2022-05-12 23:29:35 +00:00
David Harris
2d27d20db9 Cause simplification 2022-05-12 23:27:02 +00:00
David Harris
87dadc8208 trap/csr cleanup 2022-05-12 22:26:21 +00:00
David Harris
ea0d9fd9a8 More trap/csr simplification 2022-05-12 22:06:03 +00:00
David Harris
2eb6a65fa2 More trap/csr simplification 2022-05-12 22:04:20 +00:00
David Harris
2d8ccbd4ea More trap/csr simplification 2022-05-12 22:00:23 +00:00
David Harris
417e36bff5 More trap/csr simplification 2022-05-12 21:55:50 +00:00
David Harris
ca6b7716e2 Simplifying trap/csr interface 2022-05-12 21:50:15 +00:00
David Harris
56c154f2e7 Simplified MTVAL logic 2022-05-12 21:36:13 +00:00
David Harris
730bcac6ba Partitioned privileged pipeline registers into module 2022-05-12 20:45:45 +00:00
David Harris
c5868b81e4 privileged cleanup 2022-05-12 20:21:33 +00:00
mmasserfrye
517e44746e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-12 20:20:40 +00:00
mmasserfrye
2675c217e0 cleaned lint for ppa.sv 2022-05-12 20:20:05 +00:00
David Harris
5537c33196 Formatting cleanup 2022-05-12 18:37:47 +00:00
mmasserfrye
57a69d0f67 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-12 18:08:20 +00:00
mmasserfrye
30a1ba7bcf renamed madzscript, modified ppa.sv alu and shifter 2022-05-12 18:05:02 +00:00
David Harris
449472ba58 Moved Breakpoint and Ecall fault logic into privdec 2022-05-12 16:45:53 +00:00
David Harris
9f8dca5190 Moved TLB Flush logic into privdec 2022-05-12 16:41:52 +00:00
David Harris
1d01bc98a4 Moved WFI timeout into privdec 2022-05-12 16:22:39 +00:00
David Harris
21c1e58829 Partitioned privilege mode fsm into new module 2022-05-12 16:16:42 +00:00
David Harris
61199ccd13 More signal cleanup 2022-05-12 15:39:44 +00:00
David Harris
4c5e361b00 More unused signal cleanup 2022-05-12 15:26:08 +00:00
David Harris
5acb526375 More unused signal cleanup 2022-05-12 15:21:09 +00:00
David Harris
7e764fbda1 More unused signal cleanup 2022-05-12 15:15:30 +00:00
David Harris
e2dea3bb89 Removed more unused signals, simplified csri state 2022-05-12 15:10:10 +00:00
David Harris
fb725a9e0a Clean up unused signals 2022-05-12 14:49:58 +00:00
David Harris
8372bc86a7 Removing unused signals 2022-05-12 14:36:15 +00:00
David Harris
15659b05e4 Simplifed mstatus.TSR handling 2022-05-12 14:09:52 +00:00
David Harris
877c4eefd1 Fixed typo in csrm 2022-05-12 06:55:39 -07:00
mmasserfrye
cf900cf44d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-12 07:24:04 +00:00
mmasserfrye
52b0e7d567 filled in ppa.sv, madzscript.py now synthesizes in parallel in puts results in csv 2022-05-12 07:22:06 +00:00
David Harris
32f8841f79 Added MCONFIGPTR CSR hardwired to 0 2022-05-12 04:31:45 +00:00
David Harris
c738c130de merged ppa.sv 2022-05-11 18:14:16 +00:00
David Harris
e37d262e4c PPA script progress 2022-05-11 18:11:51 +00:00
mmasserfrye
70fe1184db ed 
modified ppa.sv
 2022-05-11 16:22:12 +00:00
David Harris
a8c9f504fa Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt 2022-05-11 15:08:33 +00:00
David Harris
91472eb948 Removed M suffix from interrupts because they are generated asynchronously to pipeline 2022-05-11 14:41:55 +00:00
David Harris
91b786c58d Updated PPA experiment 2022-05-10 23:09:42 +00:00
David Harris
d53e4b1b1f Initial PPA study 2022-05-10 20:48:47 +00:00
David Harris
b869190161 endian swapper 2022-05-08 06:51:50 +00:00
David Harris
8066ba45e8 Preliminary support for big endian modes. Regression passes but no big endian tests written yet. 2022-05-08 06:46:35 +00:00
David Harris
2792d77e4e Fixed bug in delegated interrupts not being taken 2022-05-08 04:50:27 +00:00
David Harris
2cdd49c7d2 WFI terminates when an interrupt is pending even if interrupts are globally disabled 2022-05-08 04:30:46 +00:00
David Harris
7024293a59 Zero'd wfiM when ZICSR not supported to fix hang in E tests 2022-05-05 15:32:13 +00:00
David Harris
66424a8246 SFENCE.VMA should be illegal in user mode 2022-05-05 15:15:02 +00:00
David Harris
866540580a SFENCE.VMA should be illegal in user mode 2022-05-05 14:59:52 +00:00
David Harris
c100c9893b wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts 2022-05-05 14:37:21 +00:00
David Harris
94459ade3d Changed WFI to stall pipeline in memory stage 2022-05-05 02:03:44 +00:00
Kip Macsai-Goren
25ad39939f put privileged tests back into rv32/64gc 2022-05-04 21:20:25 +00:00
Kip Macsai-Goren
0f70e48b6b updated makefrag and tests.vh to reflect removed tests, new names 2022-05-04 21:20:25 +00:00
David Harris
8eee0c0ca3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-03 18:32:04 +00:00
David Harris
554c2b3550 Illegal instruction fault when running FPU instruction with STATUS_FS = 0 2022-05-03 18:32:01 +00:00
David Harris
cb1a7d54a4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-03 08:53:35 -07:00
David Harris
4fbf78e049 clean up sram1p1rw; still doesn't work on Modelsim 2022.1 2022-05-03 08:31:54 -07:00
David Harris
9c4de0e9c1 FPU generates illegal instruction if MSTATUS.FS = 00 2022-05-03 11:56:31 +00:00
David Harris
dee32f70bf Switched to behavioral comparator for best PPA 2022-05-03 11:00:39 +00:00
David Harris
bc123b5564 Comparator experiments 2022-05-03 10:54:30 +00:00
David Harris
7e3f75a35d Formatting cache.sv 2022-05-03 10:53:20 +00:00
David Harris
bc132c3e20 sram1p1rw extra bits are complaining on Tera and VLSI; roll back to two always blocks to fix on Tera 2022-05-03 03:50:41 -07:00
David Harris
3f2ec0499f Rewriting sram1p1rw to combine CacheData into a single always_ff. Extra bits are still giving warning on VLSI that don't make sense. 2022-05-03 03:45:41 -07:00
David Harris
7268ff1fd4 Changed loop variable in CLINT because of error only seen on VLSI 2022-05-03 10:10:28 +00:00
Kip Macsai-Goren
e557e420b6 added missing SIE test 2022-04-29 19:54:29 +00:00
Kip Macsai-Goren
5df381e26f renamed PIE-stack tests to status-mie for clarity 2022-04-29 18:30:39 +00:00
Kip Macsai-Goren
c3ffcd0e95 removed old unused tests from wally arch tests 2022-04-28 18:14:08 +00:00
Kip Macsai-Goren
3d1e1202f3 set WFI timeout to after 16 bits of counting for all configs 2022-04-28 18:14:08 +00:00
Kip Macsai-Goren
0e5cc40360 added 32 bit versions of new tests. all but timeout wait pass regression 2022-04-28 18:14:07 +00:00
Skylar Litz
970f6c4222 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-27 10:50:19 -07:00
Skylar Litz
594db170de fix AttemptedInstructionCount from ground zero 2022-04-27 10:45:40 -07:00
David Harris
6e8b27de17 Added torture.tv test vectors 2022-04-27 13:08:36 +00:00
David Harris
ffd4713fd1 Checked in torture.tv 2022-04-27 13:06:24 +00:00
David Harris
9042844b38 Cleaned up canonical NaNs and removed denorm outputs in baby_torture.tv 2022-04-26 19:41:30 +00:00
Kip Macsai-Goren
89cce88d33 fixed incorrect configs in regression 2022-04-25 19:28:47 +00:00
Kip Macsai-Goren
0f4ca62157 added working tests to test list, updated regression for new configs 2022-04-25 19:18:15 +00:00
Kip Macsai-Goren
8ad920fcb3 fixed initial value, timing on fs bits changing after floating point instruction 2022-04-25 19:17:29 +00:00
Kip Macsai-Goren
da29193f9b removed atomic, floating point from privileged tests configs 2022-04-25 19:13:15 +00:00
Kip Macsai-Goren
7ff85258f0 added new tests to tests.vh, comented out until they pass regression 2022-04-25 18:22:44 +00:00
Kip Macsai-Goren
7fe33b2147 Lowered WFI timeout wait time for privileged configs 2022-04-25 17:47:10 +00:00
David Harris
cf1fde62fb Restored MPRV behavior per spec 2022-04-25 14:52:18 +00:00
David Harris
0ede295e88 Added dummy mstatus byte endianness fields tied to 0, mstatush register, removed UIE and UPIE depricated fields 2022-04-25 14:49:00 +00:00
David Harris
851d5e8c5e Added MTINST hardwired to 0, and added timeout of U-mode WFI 2022-04-24 20:00:02 +00:00
David Harris
16ad1e0cab Fixed InstrMisalignedFaultM mtval 2022-04-24 17:31:30 +00:00
David Harris
f1ddbb169c Improved priority order and mtval of traps to match spec 2022-04-24 17:24:45 +00:00
David Harris
03f84bf11c Extended sim time to fully boot Linux. Added comments to hazard unit 2022-04-24 13:51:00 +00:00
Kip Macsai-Goren
7bc6943527 Changed mtval for instruction misaligned fault to get address from ieuAdrM (Jal/branch target address) 2022-04-22 22:46:11 +00:00
bbracker
5e76c83309 deprecate unused LINUX_FIX_READ macro 2022-04-21 19:14:47 -07:00
bbracker
afc38abe08 change how tristate I/O is spoofed in GPIO loopback test 2022-04-21 10:31:16 -07:00
Ross Thompson
8fcd4d47b7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-21 09:52:42 -05:00
Ross Thompson
165a36acac Modified wally-pipelined.do for no trace linux sim. 2022-04-21 09:52:33 -05:00
David Harris
5c607f2b6b Simplified profile for UART boot; added warnings on UART Rx errors 2022-04-21 04:54:45 +00:00
Kip Macsai-Goren
cd53163d9a added new tests to tests.vh 2022-04-20 17:34:40 +00:00
Kip Macsai-Goren
080963c381 fixed rv32ia to support clint and GPIO for priv tests 2022-04-20 17:31:34 +00:00
Kip Macsai-Goren
510021af65 added working general trap tests to regression 2022-04-20 06:48:01 +00:00
Ross Thompson
546ef08eb2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-19 14:09:50 -05:00
David Harris
1f7a95637a Added baby torture tests 2022-04-19 15:13:06 +00:00
David Harris
a8ad7be246 Fixed WFI decoding in IFU 2022-04-18 19:02:08 +00:00
Kip Macsai-Goren
1ba328324b Added GPIO loopback to let outputs cause interrupts 2022-04-18 07:22:49 +00:00
Kip Macsai-Goren
64698aa806 Added working trap test to regression, fixed hanfling of some interrupts 2022-04-18 07:22:16 +00:00
Shreya Sanghai
fd3920b217 replaced k with bpred size 2022-04-18 04:21:03 +00:00
Shreya Sanghai
c3164f0ce1 added bpred size to wally config 2022-04-18 04:21:03 +00:00
David Harris
462158ea92 LSU name cleanup 2022-04-18 03:18:38 +00:00
Ross Thompson
a99466a487 Fixed bug I introduced by csrc cleanup and changes to ILA. 2022-04-17 21:45:46 -05:00
David Harris
4a7effaf9e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-04-18 01:30:11 +00:00
David Harris
2882460c94 Renamed FinalAMOWriteDataM to AMOWriteDataM 2022-04-18 01:30:03 +00:00
David Harris
861fbd698b Run 4M instructions in buildroot test to get through kernel & VirtMem startup 2022-04-18 01:29:38 +00:00
Ross Thompson
c045e3afd8 Added back the instret counter to ILA. 2022-04-17 18:44:07 -05:00
Ross Thompson
c409bde6ae fixed no forcing bug in linux testbench. 2022-04-17 17:49:51 -05:00
David Harris
2819a1c305 Remvoed bytemask anding from FinalWriteDataM in subwordwrite 2022-04-17 22:33:25 +00:00
David Harris
812b56acc6 Prefix comparator cleanup 2022-04-17 21:53:11 +00:00
David Harris
de5b61291f Experiments with prefix comparator; minor fixes in WFI and testbench warnings 2022-04-17 21:43:12 +00:00
Kip Macsai-Goren
1f9c987efe added new tests to makefrag and tests.vh 2022-04-17 21:00:36 +00:00
Ross Thompson
059c04e2a8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-17 15:23:46 -05:00
Ross Thompson
c16dec88de Increased uart baud rate to 230400. 
Added uart signals to debugger.
 2022-04-17 15:23:39 -05:00
David Harris
2436534687 First implementation of WFI timeout wait 2022-04-17 17:20:35 +00:00
David Harris
83d283354c Added comments in fcvt 2022-04-17 16:53:10 +00:00
David Harris
aa1bac361d Simplified SLT logic 2022-04-17 16:49:51 +00:00
Ross Thompson
238cc9f9fd Commented output power analysis to speed simulation. 2022-04-16 15:32:59 -05:00
Ross Thompson
16b3c64234 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-16 14:59:03 -05:00
Ross Thompson
b9a19304db Fixed possible bugs in LRSC. 2022-04-16 14:45:31 -05:00
David Harris
68d9c99fba Added WFI support to IFU to keep it in the pipeline 2022-04-14 17:26:17 +00:00
David Harris
a28831b83e Added WFI to the testbench instruction name decoder 2022-04-14 17:12:11 +00:00
David Harris
855d68afde WFI should set EPC to PC+4 2022-04-14 17:05:22 +00:00
bbracker
fe53dd1683 fix testbench timing bug where interrupt forcing didn't happen soon enough because it was waiting on StallM 2022-04-14 09:23:21 -07:00
bbracker
eb21e34000 fix ReadDataM forcing 2022-04-13 15:32:00 -07:00
Ross Thompson
2e8afd071e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-13 13:39:47 -05:00
bbracker
5de92af0b1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-13 05:35:56 -07:00
bbracker
735c75af55 change interrupt spoofing to happen at negative clock edges 2022-04-13 04:31:23 -07:00
bbracker
52ed99ca1b improve testbench-linux.sv to correctly load in PLIC IntEnable checkpoint and to handle edge case where interrupt is caused by enabling interrupts in SSTATUS 2022-04-13 03:37:53 -07:00
bbracker
03f1c01f14 whoops forgot to update AttemptedInstructionCount in interrupt spoofing 2022-04-13 00:49:37 -07:00
bbracker
d3e9703c19 change testbench-linux to by default use attempted instruction count for warning/error messages 2022-04-12 21:22:08 -07:00
Ross Thompson
bb6f1cf816 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-12 19:38:04 -05:00
Ross Thompson
fc173a7954 Missed the force on uart for no tracking. 2022-04-12 19:37:44 -05:00