Commit Graph

3622 Commits

Author SHA1 Message Date
James Stine
46bf9c351c Update C program for r=4 division by recurrence to match Table in EL 2022-06-20 11:32:40 -05:00
Daniel Torres
d23df0bde8 graph generator now generates 4 graphs, with space for 4 more 2022-06-17 21:28:28 -07:00
Daniel Torres
397783812d embench and testbench now support running both O2 and Os build variations without overwriting one another 2022-06-17 21:15:42 -07:00
Daniel Torres
196b43d113 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-17 20:53:19 -07:00
Daniel Torres
1d4c543f71 arch tests now run on spike and sail and compare signatures during build 2022-06-17 20:53:15 -07:00
Madeleine Masser-Frye
f807c70cdc Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
removing runArchive and plots directories from synthDC history
2022-06-18 00:13:30 +00:00
Madeleine Masser-Frye
b538feb228 Create test2 2022-06-17 23:22:04 +00:00
Daniel Torres
6f381171de Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-17 15:50:10 -07:00
Daniel Torres
0ede7c412e removed old code from makefile, simplified code in testbench 2022-06-17 15:13:38 -07:00
Daniel Torres
475220a5ff arch bug fixes and testbench changes 2022-06-17 15:07:16 -07:00
Madeleine Masser-Frye
59a514ae81 remove run deletion with wally synthesis 2022-06-17 19:45:38 +00:00
Madeleine Masser-Frye
dfae71066e error calculation function, fixed energy units 2022-06-17 19:36:32 +00:00
Madeleine Masser-Frye
8449029bf3 latest synths and synth script 2022-06-17 19:34:58 +00:00
Daniel Torres
cd56d256ad added new work files to gitignore 2022-06-16 18:06:25 -07:00
Daniel Torres
8b6b0009a6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-16 18:05:18 -07:00
Daniel Torres
83cce676a0 added files needed for arch to build 2022-06-16 18:05:06 -07:00
Katherine Parry
2a8c17170c hopefully fixed lint error 2022-06-17 00:14:39 +00:00
Katherine Parry
c9cbf6082d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-15 22:58:42 +00:00
Katherine Parry
0ffaec850b postprocess out of fpu critical path 2022-06-15 22:58:33 +00:00
Madeleine Masser-Frye
154a1c80c1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-15 18:30:27 +00:00
Madeleine Masser-Frye
84256924e7 cleanup, plots for paper 2022-06-15 18:28:36 +00:00
Madeleine Masser-Frye
74c527a818 fresh set of syntheses 2022-06-15 18:26:16 +00:00
James Stine
c660403ff2 Add back SV for integer division to use 8-bit CPA in qslc 2022-06-15 11:46:39 -05:00
James Stine
a078015271 Add r=4 C code 2022-06-15 11:44:09 -05:00
Katherine Parry
08b2481917 some synth fpu optimizations 2022-06-14 23:58:39 +00:00
DTowersM
97d4368780 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-14 17:08:48 +00:00
DTowersM
c0b9a1b24e fixed a typo in makefile 2022-06-14 17:08:39 +00:00
Katherine Parry
8e19331ad5 removed false critical path from fpu 2022-06-14 16:50:46 +00:00
Katherine Parry
674c31ce59 fixed acciedental critical path in FPU 2022-06-14 00:02:38 +00:00
DTowersM
7c0f4dd954 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-13 23:34:35 +00:00
DTowersM
a229e0ee87 fixed typo in git ignore 2022-06-13 23:34:27 +00:00
DTowersM
12f465ea05 added back the .git ignore and .git modules for the coremark directory, also added graphGen to the main repo 2022-06-13 23:33:10 +00:00
DTowersM
39ed36d0ba added back working coremark in benchmarks/riscv64-bcoremarkdirectory, experimental simplifications are in benchmarkscoremark/ but this doesn't currently work (some type of c bug) 2022-06-13 23:23:57 +00:00
Katherine Parry
5f7072bd96 postprocessing unit created and passing all tests 2022-06-13 22:47:51 +00:00
David Harris
802bfd74fb Cleanup on RAM module 2022-06-13 19:37:43 +00:00
David Harris
3c44b5842b Typo in gpio reset 2022-06-13 19:37:05 +00:00
slmnemo
3626d5880e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-13 12:30:33 -07:00
David Harris
9e1ec0255f Removed SRT testvectors from repo 2022-06-13 19:27:33 +00:00
slmnemo
05a217c7e7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-13 12:27:23 -07:00
slmnemo
c5d2037a7f Merge branch 'cacheburstmode' into main.
Cache burst mode is now working! It also uses the new RAM.
2022-06-13 12:26:18 -07:00
slmnemo
a21d731834 Added more comments 2022-06-13 12:26:08 -07:00
David Harris
9080e35e54 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-13 19:26:07 +00:00
David Harris
09d72a33c5 Fixed XOR logic in GPIO 2022-06-13 19:26:03 +00:00
slmnemo
9f4ca06f7f Added comment about name of LSUBusInit/Lock signal 2022-06-13 10:56:02 -07:00
slmnemo
a79737e95b Removed irrelevant comments in ahblite and made it more clear when to use certain transmission signals 2022-06-10 20:43:56 -07:00
slmnemo
d6a1ee1141 Added comments to signals added so the bus is easier to analyze 2022-06-10 20:30:04 -07:00
slmnemo
31852fdb19 Fixed failed regression state by only enabling counting when doing cached operations 2022-06-10 20:00:09 -07:00
slmnemo
0e10435fb6 Fixed error where CntReset would be high one cycle too long, adding a cycle of delay. Broke wally64priv by failing trap-sret-01. 2022-06-10 19:10:01 -07:00
Madeleine Masser-Frye
032385aee3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-10 21:11:47 +00:00
Madeleine Masser-Frye
1d03948d33 equation table, plot adjustments 2022-06-10 21:11:39 +00:00