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1160 Commits

Author SHA1 Message Date
Noah Limpert
cb77c1db3a updated fpu instantion on wallypiplinedhart to remove .*, updated spacing as well 2021-11-24 23:22:04 -08:00
Noah Limpert
e66fdd3f80 replaced .* instation of priv module on wallypiplinedhart 2021-11-24 22:58:59 -08:00
Noah Limpert
0cd31bfc1f Made abhlite instation on wallypipehart more clear, updated spacing for consistency 2021-11-24 22:48:01 -08:00
Noah Limpert
8a64510ee4 updated module instation of LSU on wallypiplinedhard 2021-11-24 22:09:39 -08:00
Ross Thompson
b909375289 Missed another change to uart. 2021-11-23 10:20:47 -06:00
Ross Thompson
fe00729d7c Fixed syntax error which modelsim did not detect in my changes for making uart work with qemu's simulation. 2021-11-23 10:00:32 -06:00
Ross Thompson
e309017ec4 Added QEMU hack for initial LCR value in uart. 2021-11-22 15:23:19 -06:00
Ross Thompson
e568068c78 Hack added to uart so QEMU simulation can work with an ultra fast baud rate relative to the clock speed. 2021-11-22 15:20:54 -06:00
Ross Thompson
fcd14828d4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-11-22 11:30:14 -06:00
bbracker
d90d708cf9 activate STVAL for buildroot 2021-11-21 10:40:28 -08:00
Ross Thompson
c661bb4894 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-11-20 22:44:45 -06:00
Ross Thompson
baa98e7015 Reversed bit order in uart. 2021-11-20 22:43:05 -06:00
Ross Thompson
2f85ac7f38 Fixed a very complex interaction between interrupts, the icache, dcache, and hptw. 
If an interrupt occurred at the start of an ITLB miss or DTLB miss the page table
walk should be aborted before starting.
 2021-11-20 22:35:47 -06:00
slmnemo
870549c01a Removed .* from hazard hzu(.*). 2021-11-17 14:21:23 -08:00
slmnemo
a98dcd11ee Removed .* from hazard hzu(.*) in wallypipelinedhart.sv. 2021-11-17 14:08:08 -08:00
slmnemo
fed613dc72 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-17 13:38:51 -08:00
slmnemo
f4380faa4e removed .* from muldiv.sv (REAL) 2021-11-17 13:37:50 -08:00
Noah Limpert
0ccc7d5fe8 ieu variable naming changed for clarity 2021-11-17 13:24:28 -08:00
slmnemo
9fb26d5a61 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-17 13:23:20 -08:00
slmnemo
573f8b0c42 Removed .*s from muldiv.sv 2021-11-17 13:23:12 -08:00
Noah Limpert
832b23b8a4 Updated IFU variable naming for clarity 2021-11-17 12:39:05 -08:00
Kip Macsai-Goren
3f76549a7d renamed presrc to forwardedSrc, replaced SrcAE and SrcBE with Forwarded src in the muldiv 2021-11-17 10:53:17 -08:00
Ross Thompson
3b8bdc7b2d Created separate memory interface for the ddr4 fpga memory from the soc internal memory dtim. 2021-11-17 12:47:19 -06:00
Ross Thompson
11a21899d5 Fixed uart by reversing the bit order on transmit. 
Set prescale to 0.
 2021-11-17 10:32:41 -06:00
Ross Thompson
4af7a27d87 Have linux booting. Not sure about uart, but uart is now part of the ILA and I can see TX changing. 2021-11-12 17:37:07 -06:00
Ross Thompson
b8572d6a2a Changed several things. 
Removed the need to use async flip flops in SDC.
Added arrs, a synchronizer for reset.
I think this works with the real FPGA hardware.
The last build did not include this arrs but it worked.
 2021-11-12 11:13:50 -06:00
Kevin
b34569c358 changed code aligner to run recursively on a root directory 
-only runs the aligner on .sv files
-runs recursively on sub-directories
 2021-11-03 10:49:34 -07:00
David Harris
4b57af9cff PIPELINE test running 2021-11-01 12:44:35 -07:00
Ross Thompson
8aad95366d Fixed the 4 way set associative pseudo LRU replacement policy. 2021-10-29 12:46:02 -05:00
Ross Thompson
f61fcd25a9 Possible fix for the incorrect behavior of the pseudo LRU replacement policy for 4 ways set associative caches. 2021-10-29 11:03:37 -05:00
Ross Thompson
54c714d222 Applied batch from fpga branch which fixes the dcache fence bug. The should cause the dcache to flush all dirty cache lines to main memory. The bug caused the dirty reset to clear each way for a particular line. 2021-10-28 11:07:18 -05:00
Noah Limpert
21ea270fe2 Have replaced .* with signal names in ifu 2021-10-27 13:45:37 -07:00
koooo142857
0a33b0904d aligned all files in ifu folder 2021-10-27 12:43:55 -07:00
David Harris
9cfb8deaab Fixed FResultSelM to select proper flags 2021-10-27 11:02:42 -07:00
Ross Thompson
d98baf90a3 Replaced async reset flip flops with sync reset flip flops in cache and bpread. 2021-10-27 09:57:11 -05:00
Ross Thompson
0817ef20f1 Linux now boots fpga. 2021-10-26 16:49:16 -05:00
David Harris
1a6fb2fad9 Forgot to save cacheway merge 2021-10-26 08:38:13 -07:00
David Harris
79c1395967 merging changes 2021-10-26 08:34:36 -07:00
David Harris
44de52a05a Synchronous reset in non-flop blocks 2021-10-26 08:30:35 -07:00
Ross Thompson
09b3549efd Fixed another critical path in the caches. 2021-10-25 22:05:11 -05:00
Ross Thompson
cb7015a690 Fixed the timing issue in the cache replacement polcy. 2021-10-25 18:00:23 -05:00
Ross Thompson
6c92d3267f Fixed bug with the changes to sram1rw. 2021-10-25 16:11:41 -05:00
Ross Thompson
c963ea1a64 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-25 15:36:21 -05:00
Ross Thompson
694b3fbb6f Possible fix for critical path timing in caches. 2021-10-25 15:33:33 -05:00
Ross Thompson
2f4ee26b60 Fixed issue with dtim (fpga) external abhlite select not triggering. 
Setup the bootloader (bios.s) to copy 127MB and blink LEDs for 5 seconds with 1 second period.
 2021-10-25 14:51:54 -05:00
bbracker
2c9c9328a9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-25 12:25:37 -07:00
Ross Thompson
f7583d0e0d Updated uncore to use sdc. 
Fixed bug with fence instruction not correctly clearing dirty bits in d cache.
 2021-10-25 14:07:44 -05:00
David Harris
14e6d2c576 Converted flops to synchronous reset now that reset signal is synchronized 2021-10-25 11:49:20 -07:00
David Harris
47124f36c8 Added synchronizer to reset 2021-10-25 10:05:41 -07:00
Ross Thompson
ebef47b1c9 Modified the cache's sram model so if it used to synthesize flip flops it terminates the read critical path at the address's input rather than the output read data. 2021-10-24 21:21:49 -05:00
bbracker
eb9740bc31 manually resolved git merge conflicts in testbench linux after checkpointing 2021-10-24 15:02:19 -07:00
Ross Thompson
87aaec3b6c Partial cleanup of unused signals in caches and bpred. 2021-10-24 15:04:20 -05:00
bbracker
dcd4d9dd9f add checkpointing to linux testbench 2021-10-24 06:47:35 -07:00
David Harris
106982e493 more lsu/ifu lint cleanup 2021-10-23 12:10:13 -07:00
David Harris
8b1dc81d34 more lsu/ifu lint cleanup 2021-10-23 12:00:32 -07:00
David Harris
88b2d9e687 lsu/ifu lint cleanup 2021-10-23 11:41:20 -07:00
David Harris
d0aa6911ff random lint cleanup 2021-10-23 11:24:36 -07:00
David Harris
bb4ad264ce IEU cleanup 2021-10-23 11:13:28 -07:00
David Harris
b6bb33ecef lint cleanup 2021-10-23 11:03:28 -07:00
David Harris
5e961973cb IEU lint cleanup 2021-10-23 10:51:53 -07:00
David Harris
708b914a65 Lint cleanup from wallypipeliendhart 2021-10-23 10:29:52 -07:00
David Harris
817795f619 Lint cleanup: ahblite, ifu, hart 2021-10-23 10:12:33 -07:00
David Harris
2abec36221 Lint cleanup 2021-10-23 09:58:52 -07:00
David Harris
6ae9aa7d80 lint cleanup: FPU and privileged 2021-10-23 09:41:24 -07:00
David Harris
80d2b9bc0d subword read and csrc lint cleanup 2021-10-23 09:29:15 -07:00
David Harris
0eabd0ecc2 FMA and CSRC lint cleanup 2021-10-23 09:20:24 -07:00
David Harris
5235e61d9e Lint cleanup 2021-10-23 09:06:21 -07:00
David Harris
bf3eb7b814 update scripts for handling src/*/* subdirectories 2021-10-23 08:54:29 -07:00
David Harris
7732d38c36 lint cleaning and moved files into subdirectories 2021-10-23 08:53:32 -07:00
David Harris
ff409d4fe7 Lint cleanup 2021-10-23 08:39:21 -07:00
David Harris
8b854bb1c2 Cleaned up LINT erors 2021-10-23 06:28:49 -07:00
David Harris
5142bfd624 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-23 06:15:49 -07:00
David Harris
3407b63c8a Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience. 2021-10-23 06:15:26 -07:00
Ross Thompson
6bad4058eb Merge branch 'main' into fpga 2021-10-22 16:09:16 -05:00
James E. Stine
a60e19dc3f Modify register before fpdivsqrt to be synthesizable for FPGAs and better in tune for ASIC clocking 2021-10-22 13:41:50 -05:00
Katherine Parry
00cc1e0c5c put the FMA priority encoders into their own module 2021-10-22 10:03:12 -07:00
James E. Stine
0e0a107a98 Get rid of lint warning - still need more testing though 2021-10-21 15:19:22 -05:00
James E. Stine
49721a169b Clean up some FPU and add pipelined fpdivsqrt to fpu.sv 2021-10-21 13:52:12 -05:00
James E. Stine
129ef03b2d Fix fpdivsqrt lint error on CPA for convergence 2021-10-20 17:46:13 -05:00
Ross Thompson
09dc3e1143 Merge branch 'main' into fpga 2021-10-20 16:24:55 -05:00
Ross Thompson
f4e64c2eaf Added debug signals to dcache. 2021-10-20 15:52:05 -05:00
David Harris
687703f0d8 removed .* from wallypipeliendsoc 2021-10-20 13:49:18 -07:00
James E. Stine
7536e0a2ee Added pipelined version of fpdivsqrt as well as analysis of fpdivsqrt to cut multiplier down to 60bits. 2021-10-20 12:00:41 -05:00
James E. Stine
ed179b0bd9 Some more sanitization but will pass to legal to determine if okay on version - it is substantially different in some ways but not a legal expert on this 2021-10-19 12:09:43 -05:00
James E. Stine
b65a4bd040 Modify DW02_multp to properly list the correct number of bits at the output (i.e., 2*WIDTH + 2). 2021-10-19 11:58:06 -05:00
Ross Thompson
77a89c30de Fixed bug with the external memory region selection. 
Updated bios program to copy just 127MB to dram.
 2021-10-19 11:23:23 -05:00
David Harris
8d08ca6a1e Changed some flops to settable 2021-10-18 17:05:29 -07:00
David Harris
df0b65e483 replaced flopenl with flopenr when clearing to 0 2021-10-18 16:53:18 -07:00
David Harris
d0b9ebd2ef Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-18 15:44:31 -07:00
David Harris
47f7a5db9c Fixed multiplier and pointed arch tests to new path in addins 2021-10-18 15:43:59 -07:00
Ross Thompson
d8d414665c fixed issues with dc shell not liking modules with parameters without default values. 2021-10-18 17:24:15 -05:00
James E. Stine
d895fd7ee5 Sanitization some more on mult_cs.sv 2021-10-18 05:24:16 -05:00
James E. Stine
aafa988ca2 Update some on mult_cs and delete DW02_mult.v 2021-10-18 05:06:49 -05:00
James E. Stine
5a1835622c Add hacky hand-made carry/save multiplier - will improve 2021-10-16 10:37:29 -05:00
Katherine Parry
33e5a078bf cvtfp module documented 2021-10-14 15:25:31 -07:00
James E. Stine
6b30adb309 Clean up some signals - beautification onging 2021-10-14 17:12:00 -05:00
Skylar Litz
395e070917 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-13 15:38:32 -07:00
Skylar Litz
d639222519 add StallM signal back to DivStartE control 2021-10-13 15:34:40 -07:00
James E. Stine
eb64a7f0c9 Update to fpdivsqrt to go on posedge as it should. Also an update to 
individual regression test for TestFloat (still needs some tweaking)
 2021-10-13 17:14:42 -05:00
Katherine Parry
09f51871c5 lint warnings fixed 2021-10-12 09:45:02 -07:00