Jordan Carlin
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b707b12267
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Merge branch 'main' of https://github.com/openhwgroup/cvw into wsim_flags
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2024-12-06 19:27:59 -08:00 |
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Huda-10xe
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c1eab9e778
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Updates to WallyTracer
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2024-12-05 06:55:23 -08:00 |
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Huda-10xe
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617434ac32
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Changes to Tracer for VM covergae
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2024-12-05 00:04:58 -08:00 |
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Rose Thompson
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3c848cd16c
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Fixed bug in the wally tracer to support hptw pte accesses.
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2024-12-03 09:56:03 -06:00 |
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Huda-10xe
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54e09df77c
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Removing debug signals
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2024-12-03 04:10:22 -08:00 |
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Huda-10xe
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ffdaca2760
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Removing debug signals
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2024-12-03 04:09:11 -08:00 |
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Huda-10xe
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4591d625d5
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Added another signal for VM Coverage
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2024-12-03 03:56:30 -08:00 |
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Jordan Carlin
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783b81f8b8
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VCD support in all simulators
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2024-12-02 13:52:44 -08:00 |
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Jordan Carlin
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1932d8bc5d
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Update testbench makefile to generate memfile even in elf file does not end in .elf
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2024-12-01 17:56:16 -08:00 |
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David Harris
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ec3143f014
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Updated warning in ramxdetector
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2024-11-29 12:03:14 -08:00 |
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David Harris
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155d1d511b
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Fixed funct7 code for sinval.vma (issue #1154)
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2024-11-29 11:39:24 -08:00 |
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David Harris
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05189d102a
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Modifying tracer toward being able to run non-gc configurations in lockstep
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2024-11-26 22:09:11 -08:00 |
|
David Harris
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028ffe9f4a
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Removing obsolete ***
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2024-11-20 07:23:51 -08:00 |
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David Harris
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ce7b036b78
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Merge pull request #1109 from jordancarlin/lint
More lint cleanup: remove unused params
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2024-11-16 16:34:15 -08:00 |
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Jordan Carlin
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00d02e5656
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fix testbench
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2024-11-16 12:53:10 -08:00 |
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Jordan Carlin
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2b57633217
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Switch to out of tree riscv-arch-test with VM tests + add pmp & vm tests to testbench
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2024-11-15 22:52:21 -08:00 |
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Rose Thompson
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fcf4ca1417
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Disabled tracer print.
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2024-11-15 08:32:43 -06:00 |
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Rose Thompson
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3596be433c
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Fixed the tracer so that traps don't clear the instruction or PC bits.
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2024-11-15 08:31:19 -06:00 |
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David Harris
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c02a649c3b
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Fixed warnings related to tracer variables
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2024-11-15 05:33:16 -08:00 |
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Huda-10xe
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b2789f304a
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Removing old code (not in use anymore)
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2024-11-15 00:39:16 -08:00 |
|
Jordan Carlin
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9d2a5c6e03
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Fix wallyTracer bug
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2024-11-14 15:31:10 -08:00 |
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Jordan Carlin
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51d7eea98a
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Merge branch 'main' of https://github.com/openhwgroup/cvw into rvvi32
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2024-11-14 15:04:11 -08:00 |
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Jordan Carlin
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61c5d035e9
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Add mseccfg shell to wallyTracer and reformat CSRs
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2024-11-14 15:03:13 -08:00 |
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Rose Thompson
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5e4f4c2072
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Simple change to ensure Trapped instructions are included with rvvi as
valid instructions. Required for functional coverage.
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2024-11-14 16:14:02 -06:00 |
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Jordan Carlin
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14e9a39523
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pmps working for RVVI in RV32
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2024-11-13 22:12:11 -08:00 |
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Jordan Carlin
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d666a0dd7b
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Update formatting in an attempt to understand what's happening in this file
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2024-11-13 18:26:53 -08:00 |
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Jordan Carlin
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017b3e9872
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Fix 32 bit CSRs in wallyTracer
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2024-11-13 17:01:01 -08:00 |
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Rose Thompson
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77d47e531f
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Merge branch 'main' into lrufixes
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2024-11-13 10:34:21 -06:00 |
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Rose Thompson
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2fe73f8174
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Replaced double | and & with single. We were having issues with these verilator giving a warning about the parameter widths not matching. However the warning is not occuring anymore.
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2024-11-13 00:02:51 -06:00 |
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Rose Thompson
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8993432928
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Resolved issue with questa not liking the TEST +arg as a generate.
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2024-11-12 23:57:30 -06:00 |
|
Rose Thompson
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ef7072b7c2
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Merge branch 'main' into lrufixes
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2024-11-12 17:57:28 -06:00 |
|
Rose Thompson
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8659d6efdb
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Resolved all CacheSim.py vs Wally mismaches.
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2024-11-12 17:24:06 -06:00 |
|
Rose Thompson
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57fbd35484
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Fixed lint errors in loggers.sv with Kaitlin.
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2024-11-12 15:03:30 -06:00 |
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Rose Thompson
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b7b7c79726
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CBO.FLUSH was not clearing the valid bit if the cacheline was clean.
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2024-11-12 14:16:55 -06:00 |
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Rose Thompson
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5cc1fd4a85
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Getting closer. Oly the wally64priv tests mismatch between the cachesim and wally.
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2024-11-12 12:08:14 -06:00 |
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Rose Thompson
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8a4868ac57
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Resolved a bug in the cache but there are still mismatches with the cache simulator.
|
2024-11-12 11:35:29 -06:00 |
|
Rose Thompson
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0cf7b2e45a
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Progress on fixing the cache simulator to support cbo instructions.
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2024-11-11 16:37:17 -06:00 |
|
Rose Thompson
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1629eda608
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Added btbthrash to tests.vh.
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2024-10-30 16:07:05 -05:00 |
|
David Harris
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0555e58afe
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Removed unnecessary display statement from testbench for DTIM versions
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2024-10-26 02:12:43 -07:00 |
|
Rose Thompson
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8fb1673ab3
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Updated email address authorship for my files.
|
2024-10-15 10:27:53 -05:00 |
|
Rose Thompson
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2ef7005ea6
|
Fixed name of test and added to tests.vh
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2024-10-13 15:29:27 -05:00 |
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Huda-10xe
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b77df83b59
|
Adding DUT signals to the tracer for VM Coverage
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2024-10-07 03:52:36 -07:00 |
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Huda-10xe
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24f97fa696
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Adding DUT signals to the tracer for VM Coverage
|
2024-10-07 03:49:43 -07:00 |
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Huda-10xe
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e0ea37fe21
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Merge branch 'main' of https://github.com/openhwgroup/cvw into rvvi_setup
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2024-10-07 03:44:43 -07:00 |
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Huda-10xe
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0817c69152
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Adding priv coverage to ISACOV
|
2024-10-07 03:44:35 -07:00 |
|
Rose Thompson
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9139f91c56
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Updated tests.vh to include floatmisc into coverage64gc. And removed
all tests from custom suite. These should be run individually.
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2024-10-02 17:21:22 -05:00 |
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Rose Thompson
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083e583877
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Added extra $display to print the test name during coverage.
|
2024-10-02 15:41:14 -05:00 |
|
Rose Thompson
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6ad27a436c
|
Updated coverage64gc test suite to include new tlb, hptw, and amo
fault tests.
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2024-10-02 15:29:50 -05:00 |
|
Jordan Carlin
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23f037e76e
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Add misaligned cjal and cjalr tests
|
2024-09-29 22:33:11 -07:00 |
|
Jordan Carlin
|
8a58f9556e
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Merge branch 'main' of https://github.com/openhwgroup/cvw into arch-test-update
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2024-09-29 17:16:05 -07:00 |
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