Ross Thompson
fe00729d7c
Fixed syntax error which modelsim did not detect in my changes for making uart work with qemu's simulation.
2021-11-23 10:00:32 -06:00
Ross Thompson
e309017ec4
Added QEMU hack for initial LCR value in uart.
2021-11-22 15:23:19 -06:00
Ross Thompson
e568068c78
Hack added to uart so QEMU simulation can work with an ultra fast baud rate relative to the clock speed.
2021-11-22 15:20:54 -06:00
Ross Thompson
fcd14828d4
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-11-22 11:30:14 -06:00
bbracker
d90d708cf9
activate STVAL for buildroot
2021-11-21 10:40:28 -08:00
Ross Thompson
c661bb4894
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-11-20 22:44:45 -06:00
Ross Thompson
d080041508
Removed unneeded check for icache ways.
2021-11-20 22:44:37 -06:00
Ross Thompson
baa98e7015
Reversed bit order in uart.
2021-11-20 22:43:05 -06:00
Ross Thompson
4443fca5c5
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-11-20 22:37:15 -06:00
Ross Thompson
2f85ac7f38
Fixed a very complex interaction between interrupts, the icache, dcache, and hptw.
...
If an interrupt occurred at the start of an ITLB miss or DTLB miss the page table
walk should be aborted before starting.
2021-11-20 22:35:47 -06:00
bbracker
9e4033935f
add checkpoints to regression
2021-11-20 19:42:53 -08:00
bbracker
685534fc20
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-19 20:25:06 -08:00
bbracker
42ba205c4f
automatic bug finder script
2021-11-19 20:25:00 -08:00
bbracker
5a2a2ca4f5
increase buildroot progress expecttions; increase timeout to 20 hours
2021-11-19 12:52:11 -08:00
David Harris
fb3f267645
Coremark Cleanup, trying compile from addins
2021-11-19 06:09:04 -08:00
David Harris
c45f276f86
Moved exe2memfile.pl
2021-11-18 20:32:13 -08:00
David Harris
d243f4bcd1
Cleaning up CoreMark benchmark
2021-11-18 20:12:52 -08:00
David Harris
54fef3e2ca
vert "Simplifying riscv-coremark"
...
This reverts commit bdc212cf88
2021-11-18 18:40:13 -08:00
David Harris
bdc212cf88
Simplifying riscv-coremark
2021-11-18 17:15:40 -08:00
David Harris
f2cf09dd76
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-18 16:14:42 -08:00
David Harris
b996598b37
CoreMark testing
2021-11-18 16:14:25 -08:00
slmnemo
870549c01a
Removed .* from hazard hzu(.*).
2021-11-17 14:21:23 -08:00
slmnemo
a98dcd11ee
Removed .* from hazard hzu(.*) in wallypipelinedhart.sv.
2021-11-17 14:08:08 -08:00
slmnemo
fed613dc72
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-17 13:38:51 -08:00
slmnemo
f4380faa4e
removed .* from muldiv.sv (REAL)
2021-11-17 13:37:50 -08:00
David Harris
b49c419d0b
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-17 13:28:33 -08:00
Noah Limpert
0ccc7d5fe8
ieu variable naming changed for clarity
2021-11-17 13:24:28 -08:00
slmnemo
9fb26d5a61
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-17 13:23:20 -08:00
slmnemo
573f8b0c42
Removed .*s from muldiv.sv
2021-11-17 13:23:12 -08:00
Noah Limpert
ed2285b8e7
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-17 13:04:33 -08:00
Noah Limpert
832b23b8a4
Updated IFU variable naming for clarity
2021-11-17 12:39:05 -08:00
Kevin Kim
d4e9376854
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-17 12:18:25 -08:00
Kevin Kim
34b3cc1c8d
root level makefile added
2021-11-17 12:17:56 -08:00
Kip Macsai-Goren
3f76549a7d
renamed presrc to forwardedSrc, replaced SrcAE and SrcBE with Forwarded src in the muldiv
2021-11-17 10:53:17 -08:00
Ross Thompson
3b8bdc7b2d
Created separate memory interface for the ddr4 fpga memory from the soc internal memory dtim.
2021-11-17 12:47:19 -06:00
Ross Thompson
11a21899d5
Fixed uart by reversing the bit order on transmit.
...
Set prescale to 0.
2021-11-17 10:32:41 -06:00
Skylar Litz
e35faa9b8a
fixed interrupt timing bug
2021-11-16 16:46:17 -08:00
David Harris
5a521e28ee
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-16 12:30:55 -08:00
bbracker
23bd24323b
get current privilege level from GDB for checkpoints
2021-11-15 14:49:00 -08:00
Ross Thompson
4af7a27d87
Have linux booting. Not sure about uart, but uart is now part of the ILA and I can see TX changing.
2021-11-12 17:37:07 -06:00
Ross Thompson
b8572d6a2a
Changed several things.
...
Removed the need to use async flip flops in SDC.
Added arrs, a synchronizer for reset.
I think this works with the real FPGA hardware.
The last build did not include this arrs but it worked.
2021-11-12 11:13:50 -06:00
Skylar Litz
99a15e7897
fix timing of delayed interrupt
2021-11-11 09:35:51 -08:00
David Harris
f96152fa31
bringing Coremark back to life
2021-11-10 12:43:31 -08:00
Kevin Kim
a7684f1b59
Makefile added in regression directory:
...
-cd's into imperas then runs make commands, finally running the tvLinker script
2021-11-09 10:55:48 -08:00
bbracker
1597e0dac6
increase expectations for buildroot and timeout count
2021-11-06 14:57:29 -07:00
bbracker
24d3244cfe
checkpoint MIDELEG support
2021-11-06 03:44:23 -07:00
bbracker
1d3d7cbe1e
fix merge conflict
2021-11-05 23:42:15 -07:00
bbracker
3077769cbd
checkpoints now use binary ram files
2021-11-05 22:37:05 -07:00
Kevin
b34569c358
changed code aligner to run recursively on a root directory
...
-only runs the aligner on .sv files
-runs recursively on sub-directories
2021-11-03 10:49:34 -07:00
bbracker
e4cf044932
fix testbench interrupt timing
2021-11-02 21:19:12 -07:00
bbracker
8563c0f016
linux testgen refactor
2021-11-01 14:09:49 -07:00
David Harris
910957704b
Add3d wally32i test
2021-11-01 13:17:49 -07:00
David Harris
4b57af9cff
PIPELINE test running
2021-11-01 12:44:35 -07:00
David Harris
c306884e2c
Adding custom Wally test infrastructure
2021-11-01 08:48:46 -07:00
bbracker
38d26e857b
fix buildroot graphical sim
2021-10-31 18:33:43 -07:00
David Harris
e9244e7a85
Fixed exe2memfile parsing of weird line in arch64d test
2021-10-30 07:26:18 -07:00
David Harris
f35b31f166
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-29 22:32:08 -07:00
David Harris
717f9d48e9
tesgen cleanup, added riscv-arch-test D tests
2021-10-29 22:31:48 -07:00
David Harris
f7acd31bcb
rearranging testgen
2021-10-29 22:28:37 -07:00
Ross Thompson
8aad95366d
Fixed the 4 way set associative pseudo LRU replacement policy.
2021-10-29 12:46:02 -05:00
Ross Thompson
f61fcd25a9
Possible fix for the incorrect behavior of the pseudo LRU replacement policy for 4 ways set associative caches.
2021-10-29 11:03:37 -05:00
Ross Thompson
54c714d222
Applied batch from fpga branch which fixes the dcache fence bug. The should cause the dcache to flush all dirty cache lines to main memory. The bug caused the dirty reset to clear each way for a particular line.
2021-10-28 11:07:18 -05:00
bbracker
fe2bf13720
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-27 14:40:31 -07:00
bbracker
d14fa074ec
checkpoint generator off-by-one error fix
2021-10-27 14:10:29 -07:00
Noah Limpert
21ea270fe2
Have replaced .* with signal names in ifu
2021-10-27 13:45:37 -07:00
koooo142857
0a33b0904d
aligned all files in ifu folder
2021-10-27 12:43:55 -07:00
David Harris
e62b57e2c2
commented out some failing FPU tests
2021-10-27 11:27:34 -07:00
David Harris
9cfb8deaab
Fixed FResultSelM to select proper flags
2021-10-27 11:02:42 -07:00
David Harris
31a2346c37
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-27 10:37:46 -07:00
David Harris
0421b7af56
Changes for floating point sims
2021-10-27 10:37:35 -07:00
Ross Thompson
fed8882aec
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-10-27 09:59:55 -05:00
Ross Thompson
d98baf90a3
Replaced async reset flip flops with sync reset flip flops in cache and bpread.
2021-10-27 09:57:11 -05:00
Ross Thompson
0817ef20f1
Linux now boots fpga.
2021-10-26 16:49:16 -05:00
bbracker
52529db40b
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-26 12:43:48 -07:00
bbracker
1409dc48a8
bugfix argument passing to GDB script; remove outdated GDB script
2021-10-26 12:43:42 -07:00
David Harris
f793dd7a5e
removed unused signal from wave.do
2021-10-26 09:02:22 -07:00
David Harris
7d516c65e7
commented out nonworking tests
2021-10-26 08:56:49 -07:00
David Harris
ca700610f8
removed referenc outputs
2021-10-26 08:51:49 -07:00
David Harris
1a6fb2fad9
Forgot to save cacheway merge
2021-10-26 08:38:13 -07:00
David Harris
79c1395967
merging changes
2021-10-26 08:34:36 -07:00
David Harris
44de52a05a
Synchronous reset in non-flop blocks
2021-10-26 08:30:35 -07:00
Ross Thompson
09b3549efd
Fixed another critical path in the caches.
2021-10-25 22:05:11 -05:00
Ross Thompson
cb7015a690
Fixed the timing issue in the cache replacement polcy.
2021-10-25 18:00:23 -05:00
Ross Thompson
6c92d3267f
Fixed bug with the changes to sram1rw.
2021-10-25 16:11:41 -05:00
Ross Thompson
c963ea1a64
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-10-25 15:36:21 -05:00
Ross Thompson
694b3fbb6f
Possible fix for critical path timing in caches.
2021-10-25 15:33:33 -05:00
bbracker
f39a509b5b
adapt testbench linux to use reset_ext
2021-10-25 13:26:44 -07:00
bbracker
f50787203f
copy / link to checkpoint 8500000 dir
2021-10-25 13:24:02 -07:00
Ross Thompson
2f4ee26b60
Fixed issue with dtim (fpga) external abhlite select not triggering.
...
Setup the bootloader (bios.s) to copy 127MB and blink LEDs for 5 seconds with 1 second period.
2021-10-25 14:51:54 -05:00
bbracker
2c9c9328a9
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-25 12:25:37 -07:00
bbracker
c61cbf9618
change CHECKPOINT to be a parameter (not a macro) so that do scripts can control it; clean up checkpoint initialization macros
2021-10-25 12:25:32 -07:00
Ross Thompson
f7583d0e0d
Updated uncore to use sdc.
...
Fixed bug with fence instruction not correctly clearing dirty bits in d cache.
2021-10-25 14:07:44 -05:00
David Harris
14e6d2c576
Converted flops to synchronous reset now that reset signal is synchronized
2021-10-25 11:49:20 -07:00
David Harris
47124f36c8
Added synchronizer to reset
2021-10-25 10:05:41 -07:00
bbracker
b51e4d504b
some linux testbench cleanup
2021-10-25 10:04:30 -07:00
Ross Thompson
ebef47b1c9
Modified the cache's sram model so if it used to synthesize flip flops it terminates the read critical path at the address's input rather than the output read data.
2021-10-24 21:21:49 -05:00
bbracker
d348ebffda
checkpoint initialization bugfix
2021-10-24 18:39:51 -07:00
bbracker
9423b90780
switch linux graphical sim over to Ross's waves
2021-10-24 18:39:23 -07:00
bbracker
9cdbd9a0bf
remove unused scripts
2021-10-24 15:19:03 -07:00
bbracker
4100ed9a7a
update debugger script to new style
2021-10-24 15:18:44 -07:00
bbracker
3c118437de
fix typo
2021-10-24 15:05:00 -07:00
bbracker
eb9740bc31
manually resolved git merge conflicts in testbench linux after checkpointing
2021-10-24 15:02:19 -07:00
bbracker
0a32d79370
checkpoint generator bugfix
2021-10-24 14:46:56 -07:00
Ross Thompson
87aaec3b6c
Partial cleanup of unused signals in caches and bpred.
2021-10-24 15:04:20 -05:00
bbracker
4544d28bc9
or actually needed to reduce expectations of buildroot
2021-10-24 06:59:34 -07:00
bbracker
23bff55c6e
increase regression's expectations of buildroot
2021-10-24 06:50:22 -07:00
bbracker
dcd4d9dd9f
add checkpointing to linux testbench
2021-10-24 06:47:35 -07:00
bbracker
35ccab0e29
revamp linux testvector generation for refactoring checkpoint generation
2021-10-24 06:14:11 -07:00
bbracker
366cb12a13
buildroot do scripts now compile flops
2021-10-23 23:14:59 -07:00
bbracker
f6911be937
add W stage signals to linux testbench
2021-10-23 14:00:53 -07:00
bbracker
3b63dde570
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-23 13:17:37 -07:00
bbracker
d6fb441666
add option for regression to do a partial execution of buildroot
2021-10-23 13:17:30 -07:00
David Harris
67f3fc9962
wrapping up lint cleanup; many unused signals removed
2021-10-23 12:15:14 -07:00
David Harris
106982e493
more lsu/ifu lint cleanup
2021-10-23 12:10:13 -07:00
David Harris
8b1dc81d34
more lsu/ifu lint cleanup
2021-10-23 12:00:32 -07:00
David Harris
88b2d9e687
lsu/ifu lint cleanup
2021-10-23 11:41:20 -07:00
David Harris
d0aa6911ff
random lint cleanup
2021-10-23 11:24:36 -07:00
David Harris
bb4ad264ce
IEU cleanup
2021-10-23 11:13:28 -07:00
David Harris
b6bb33ecef
lint cleanup
2021-10-23 11:03:28 -07:00
David Harris
5e961973cb
IEU lint cleanup
2021-10-23 10:51:53 -07:00
David Harris
708b914a65
Lint cleanup from wallypipeliendhart
2021-10-23 10:29:52 -07:00
David Harris
817795f619
Lint cleanup: ahblite, ifu, hart
2021-10-23 10:12:33 -07:00
David Harris
2abec36221
Lint cleanup
2021-10-23 09:58:52 -07:00
David Harris
6ae9aa7d80
lint cleanup: FPU and privileged
2021-10-23 09:41:24 -07:00
David Harris
80d2b9bc0d
subword read and csrc lint cleanup
2021-10-23 09:29:15 -07:00
David Harris
0eabd0ecc2
FMA and CSRC lint cleanup
2021-10-23 09:20:24 -07:00
David Harris
5235e61d9e
Lint cleanup
2021-10-23 09:06:21 -07:00
David Harris
bf3eb7b814
update scripts for handling src/*/* subdirectories
2021-10-23 08:54:29 -07:00
David Harris
7732d38c36
lint cleaning and moved files into subdirectories
2021-10-23 08:53:32 -07:00
David Harris
ff409d4fe7
Lint cleanup
2021-10-23 08:39:21 -07:00
David Harris
8b854bb1c2
Cleaned up LINT erors
2021-10-23 06:28:49 -07:00
David Harris
5142bfd624
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-23 06:15:49 -07:00
David Harris
3407b63c8a
Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience.
2021-10-23 06:15:26 -07:00
Ross Thompson
6bad4058eb
Merge branch 'main' into fpga
2021-10-22 16:09:16 -05:00
kipmacsaigoren
c2f4b49b15
removed reduntant definitions for FPU in MISA.
2021-10-22 15:18:25 -05:00
James E. Stine
a60e19dc3f
Modify register before fpdivsqrt to be synthesizable for FPGAs and better in tune for ASIC clocking
2021-10-22 13:41:50 -05:00
Katherine Parry
00cc1e0c5c
put the FMA priority encoders into their own module
2021-10-22 10:03:12 -07:00
James E. Stine
0e0a107a98
Get rid of lint warning - still need more testing though
2021-10-21 15:19:22 -05:00
James E. Stine
49721a169b
Clean up some FPU and add pipelined fpdivsqrt to fpu.sv
2021-10-21 13:52:12 -05:00
James E. Stine
129ef03b2d
Fix fpdivsqrt lint error on CPA for convergence
2021-10-20 17:46:13 -05:00
Ross Thompson
09dc3e1143
Merge branch 'main' into fpga
2021-10-20 16:24:55 -05:00
Ross Thompson
f4e64c2eaf
Added debug signals to dcache.
2021-10-20 15:52:05 -05:00
David Harris
687703f0d8
removed .* from wallypipeliendsoc
2021-10-20 13:49:18 -07:00
James E. Stine
7536e0a2ee
Added pipelined version of fpdivsqrt as well as analysis of fpdivsqrt to cut multiplier down to 60bits.
2021-10-20 12:00:41 -05:00
David Harris
4aeadaacf0
moved coemark and testsBP to tests
2021-10-20 09:10:06 -07:00
David Harris
0e4f6392d6
Move tests into subdirectory and moved wavedrom out of project
2021-10-20 09:03:21 -07:00
David Harris
8747791bb8
radix 2 SRT checkin
2021-10-19 14:08:16 -07:00
James E. Stine
ed179b0bd9
Some more sanitization but will pass to legal to determine if okay on version - it is substantially different in some ways but not a legal expert on this
2021-10-19 12:09:43 -05:00
James E. Stine
b65a4bd040
Modify DW02_multp to properly list the correct number of bits at the output (i.e., 2*WIDTH + 2).
2021-10-19 11:58:06 -05:00
Ross Thompson
77a89c30de
Fixed bug with the external memory region selection.
...
Updated bios program to copy just 127MB to dram.
2021-10-19 11:23:23 -05:00
David Harris
8d08ca6a1e
Changed some flops to settable
2021-10-18 17:05:29 -07:00
David Harris
df0b65e483
replaced flopenl with flopenr when clearing to 0
2021-10-18 16:53:18 -07:00
David Harris
d0b9ebd2ef
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-18 15:44:31 -07:00
David Harris
47f7a5db9c
Fixed multiplier and pointed arch tests to new path in addins
2021-10-18 15:43:59 -07:00
Ross Thompson
d8d414665c
fixed issues with dc shell not liking modules with parameters without default values.
2021-10-18 17:24:15 -05:00
James E. Stine
d895fd7ee5
Sanitization some more on mult_cs.sv
2021-10-18 05:24:16 -05:00
James E. Stine
aafa988ca2
Update some on mult_cs and delete DW02_mult.v
2021-10-18 05:06:49 -05:00
James E. Stine
5a1835622c
Add hacky hand-made carry/save multiplier - will improve
2021-10-16 10:37:29 -05:00
Katherine Parry
33e5a078bf
cvtfp module documented
2021-10-14 15:25:31 -07:00
James E. Stine
6b30adb309
Clean up some signals - beautification onging
2021-10-14 17:12:00 -05:00
Kip Macsai-Goren
ffcf5f5825
Fixed typo in imperas64mmu tests causing PMP tests not to run.
2021-10-14 13:42:24 -07:00
Skylar Litz
395e070917
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-10-13 15:38:32 -07:00
Skylar Litz
d639222519
add StallM signal back to DivStartE control
2021-10-13 15:34:40 -07:00
James E. Stine
eb64a7f0c9
Update to fpdivsqrt to go on posedge as it should. Also an update to
...
individual regression test for TestFloat (still needs some tweaking)
2021-10-13 17:14:42 -05:00
bbracker
886a650da4
change infrastructure to expect only 6.3 million from buildroot
2021-10-12 10:41:15 -07:00
Shreya Sanghai
d783acbbc5
added DESIGN_COMPLIER to forgotten config files
2021-10-12 10:14:04 -07:00
Katherine Parry
09f51871c5
lint warnings fixed
2021-10-12 09:45:02 -07:00
Katherine Parry
4ea56ac68b
some fpu lint warnings fixed - still working on it
2021-10-11 18:32:03 -07:00
Ross Thompson
5fdac9fa3b
Merge branch 'main' into fpga
2021-10-11 18:17:58 -05:00
Ross Thompson
c90d129498
Fixed boot loader program to start at correct address.
...
modified script which converts the ram.txt into preload text file for sdc simulation.
created script to convert ram.txt into binary to write to flash card.
added top level for solo sd card fpga.
2021-10-11 17:22:23 -05:00
Shreya Sanghai
51185478df
made redunantmul generate DW02_multp for synopsys sythnesis
2021-10-11 11:54:39 -07:00
Shreya Sanghai
295a3c7af2
actually added redundant mul
2021-10-11 11:29:13 -07:00
David Harris
f9b37c3ce1
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-11 11:21:39 -07:00
David Harris
062fbfb610
Extended lint to check rv32/64g (including fpu. Not clean yet.
2021-10-11 11:20:42 -07:00
Shreya Sanghai
324230e2f9
added redundant multiplier
2021-10-11 11:20:12 -07:00
David Harris
fc39f77cba
Starting to optimize multiplier
2021-10-11 11:06:07 -07:00
Ross Thompson
cbf4e76d1c
Fixed sdc byte and nibble orders.
2021-10-11 12:15:52 -05:00
Ross Thompson
2e0dcaaff9
Fpga simualtion files.
2021-10-11 10:24:40 -05:00
Ross Thompson
3d9d4cc03f
Partially working sd card reader.
2021-10-11 10:23:45 -05:00
David Harris
8a64675b02
intdiv cleanup
2021-10-11 08:14:21 -07:00
David Harris
a8ce4568aa
Divider FSM simplification
2021-10-10 22:24:14 -07:00
David Harris
a077735ecc
Major reorganization of regression and simulation and testbenches
2021-10-10 15:07:51 -07:00
James E. Stine
11cf3d97c5
Update to missing vectors :P and also run_all script. Also made all scripts .sh as technically run using SH
2021-10-10 15:44:01 -05:00
bbracker
50e5b0a8f4
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-10 13:12:44 -07:00
bbracker
efe9f5d857
make regression expect what buildroot is actually able to reach
2021-10-10 13:12:36 -07:00
David Harris
266c706804
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-10 12:26:15 -07:00
David Harris
77f1ae54d8
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-10 12:25:11 -07:00
bbracker
8eff03bf1a
simplify flopenrc's that didn't actually need to be flopenrc's
2021-10-10 12:25:05 -07:00
David Harris
93e6ec96a7
Divider cleanup
2021-10-10 12:24:44 -07:00
David Harris
6d2d93deeb
Simplifying divider FSM
2021-10-10 12:21:43 -07:00
David Harris
2d09994a91
Simplifying divider FSM
2021-10-10 12:21:36 -07:00
David Harris
644af40855
Moved & ~StallM from FSM into DivStartE
2021-10-10 11:49:32 -07:00
David Harris
e93014d6d8
Moved divide iteration register names to M stage
2021-10-10 11:30:53 -07:00
David Harris
e8d013b106
Simplified remainder for divide by 0
2021-10-10 11:20:07 -07:00
David Harris
94fd682cdc
divider control signal simplificaiton
2021-10-10 10:55:02 -07:00
David Harris
bfe8bf3855
Removed negedge flops from divider
2021-10-10 10:41:13 -07:00
bbracker
179223bef0
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-10 10:10:06 -07:00
bbracker
5a987cf0ca
use correct string formatting function
2021-10-10 10:09:59 -07:00
David Harris
99fd79c20b
Simplified divider sign handling
2021-10-10 08:35:26 -07:00
David Harris
eaa8be14b9
renamed DivStart
2021-10-10 08:32:04 -07:00
