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1918 Commits

Author SHA1 Message Date
David Harris
0b63c1cede Refactored IEU/ALU logic 2021-12-08 13:48:04 -08:00
Noah Limpert
e97dd080a0 updated fcmp.sv instantiation to remove x*'s 2021-12-08 13:34:33 -08:00
David Harris
a174c8b4d7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-08 12:33:59 -08:00
David Harris
5d4014d351 Refactoring ALU and datapath muxes 2021-12-08 12:33:53 -08:00
Ross Thompson
37451b8978 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-08 13:40:44 -06:00
Ross Thompson
e1249f4312 Updated coremark testbench with the extra ports from FPGA merge. 
Fixed coremark Makefile to create work directory.
 2021-12-08 13:40:32 -06:00
bbracker
4060e77b56 increase regression's expectations of buildroot to 246 million 2021-12-08 07:01:22 -08:00
slmnemo
d58f318d39 Removed .*s from wally-pipelined/src/uncore/uncore.sv 2021-12-08 01:03:02 -08:00
slmnemo
52b4802600 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-08 00:26:13 -08:00
Noah Limpert
feb21d1c4a removed .* instantiation from ieu.sv and datapth.sv in ieu folder 2021-12-08 00:24:27 -08:00
slmnemo
acacd13ffc Removed .* from mmu instance inside lsu.sv. 2021-12-08 00:15:30 -08:00
Katherine Parry
d0e708f239 FMA uses one LOA 2021-12-07 14:15:43 -08:00
bbracker
d459e35645 undo intentionally breaking commit 2021-12-07 13:43:47 -08:00
bbracker
3379b74bb2 intentionally breaking commit 2021-12-07 13:27:34 -08:00
bbracker
cf61187273 undo intentionally breaking commit 2021-12-07 13:27:06 -08:00
bbracker
69f025a642 intentionally breaking commit 2021-12-07 13:23:19 -08:00
bbracker
ec6c3bd74c 2nd attempt at making regression-wally.py able to be run from a different dir 2021-12-07 13:13:30 -08:00
bbracker
0c48725fa5 fix checkpointing so that it can find the synchronized reset signal 2021-12-07 13:12:06 -08:00
bbracker
9fc4f3bfef Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-07 11:16:51 -08:00
bbracker
0692372037 attempt to make regression-wally.py more path-independent such that git bisect can invoke it directly 2021-12-07 11:16:43 -08:00
Ross Thompson
51e2b9ea6f Added information on how to copy the linux image to flash card. 2021-12-07 13:16:38 -06:00
bbracker
8e2a9d5bbb add buildroot tv linking to make-tests.sh 2021-12-07 11:15:59 -08:00
Ross Thompson
c7be8a701e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-07 13:12:59 -06:00
Ross Thompson
8bb3d51aad Added generate around the dtim preload. 
Added readme to explain FPGA.
 2021-12-07 13:12:47 -06:00
Ross Thompson
3d829dbbd3 Fixed two issues. 
First the xci files already include the xdc constraints for each IP block. There is no need to include the xdc files explicitly.
Second the bidir buffer for the sd card was connected backwards.
 2021-12-07 12:15:50 -06:00
bbracker
ffe7cf83e5 regression.py bugfix 2021-12-06 19:32:38 -08:00
bbracker
b714490f92 add make-tests scripts 2021-12-06 15:37:33 -08:00
bbracker
d702599d56 add buildroot-only option to regression 2021-12-06 14:13:58 -08:00
bbracker
6c9db52801 linux-testvectors symlinks shouldn't be in repo, especially not in this location 2021-12-05 22:03:51 -08:00
Ross Thompson
517cae796c Fixed more constraint issues in fpga. 
Added back in the ILA.
Design does not work yet.  Stil having issues with order of automatic
clock and I/O constraint ordering.
Added back in the preload for the boottim.
 2021-12-05 15:14:18 -06:00
David Harris
19fb0aace8 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-04 20:26:01 -08:00
David Harris
83765ea3bc Added files to repo 2021-12-04 20:25:33 -08:00
Skylar Litz
a69ab3bd1b fix some interrupt timing bugs 2021-12-03 12:32:38 -08:00
Ross Thompson
755c3e6a4c Fixed buildroot to work with the fpga's merge. 2021-12-02 18:09:43 -06:00
Ross Thompson
74ffb48c0a Mostly integrated FPGA flow into main branch. Not all tests passing yet. 2021-12-02 18:00:32 -06:00
Ross Thompson
b7e8c74e61 Merge branch 'fpga' into main 2021-12-02 14:28:10 -06:00
kwan
e4f214090d .* resolved in ifu.sv 2021-12-02 10:32:35 -08:00
kwan
2a77bc8053 .* in ifu/ifu.sv eliminated 2021-12-02 09:45:55 -08:00
David Harris
e4861e11d1 Added coremark scripts to regression directory 2021-12-01 09:08:06 -08:00
David Harris
273e211660 testing push 2021-11-30 11:20:09 -08:00
Ross Thompson
d7df9c1054 Fixed uart for FPGA config after merge. This still needs some work. 2021-11-29 16:07:54 -06:00
Ross Thompson
8e4eacc18e Merge branch 'main' into fpga 2021-11-29 10:10:37 -06:00
Ross Thompson
e43aa6ead4 Merge branch 'main' into fpga 2021-11-29 10:06:53 -06:00
bbracker
c5d393fbc6 UART hack now looks at physical addresses so that it isn't bamboozled by S-mode accesses 2021-11-25 11:01:59 -08:00
Noah Limpert
cb77c1db3a updated fpu instantion on wallypiplinedhart to remove .*, updated spacing as well 2021-11-24 23:22:04 -08:00
Noah Limpert
e66fdd3f80 replaced .* instation of priv module on wallypiplinedhart 2021-11-24 22:58:59 -08:00
Noah Limpert
0cd31bfc1f Made abhlite instation on wallypipehart more clear, updated spacing for consistency 2021-11-24 22:48:01 -08:00
Noah Limpert
8a64510ee4 updated module instation of LSU on wallypiplinedhard 2021-11-24 22:09:39 -08:00
bbracker
de8e2008d2 fix parseState.py to correctly take in PMPCFG 2021-11-24 16:52:51 -08:00
Ross Thompson
b909375289 Missed another change to uart. 2021-11-23 10:20:47 -06:00
Ross Thompson
fe00729d7c Fixed syntax error which modelsim did not detect in my changes for making uart work with qemu's simulation. 2021-11-23 10:00:32 -06:00
Ross Thompson
e309017ec4 Added QEMU hack for initial LCR value in uart. 2021-11-22 15:23:19 -06:00
Ross Thompson
e568068c78 Hack added to uart so QEMU simulation can work with an ultra fast baud rate relative to the clock speed. 2021-11-22 15:20:54 -06:00
Ross Thompson
fcd14828d4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-11-22 11:30:14 -06:00
bbracker
d90d708cf9 activate STVAL for buildroot 2021-11-21 10:40:28 -08:00
Ross Thompson
c661bb4894 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-11-20 22:44:45 -06:00
Ross Thompson
d080041508 Removed unneeded check for icache ways. 2021-11-20 22:44:37 -06:00
Ross Thompson
baa98e7015 Reversed bit order in uart. 2021-11-20 22:43:05 -06:00
Ross Thompson
4443fca5c5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-11-20 22:37:15 -06:00
Ross Thompson
2f85ac7f38 Fixed a very complex interaction between interrupts, the icache, dcache, and hptw. 
If an interrupt occurred at the start of an ITLB miss or DTLB miss the page table
walk should be aborted before starting.
 2021-11-20 22:35:47 -06:00
bbracker
9e4033935f add checkpoints to regression 2021-11-20 19:42:53 -08:00
bbracker
685534fc20 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-19 20:25:06 -08:00
bbracker
42ba205c4f automatic bug finder script 2021-11-19 20:25:00 -08:00
bbracker
5a2a2ca4f5 increase buildroot progress expecttions; increase timeout to 20 hours 2021-11-19 12:52:11 -08:00
David Harris
fb3f267645 Coremark Cleanup, trying compile from addins 2021-11-19 06:09:04 -08:00
David Harris
c45f276f86 Moved exe2memfile.pl 2021-11-18 20:32:13 -08:00
David Harris
d243f4bcd1 Cleaning up CoreMark benchmark 2021-11-18 20:12:52 -08:00
David Harris
54fef3e2ca vert "Simplifying riscv-coremark" 
This reverts commit bdc212cf88.
 2021-11-18 18:40:13 -08:00
David Harris
bdc212cf88 Simplifying riscv-coremark 2021-11-18 17:15:40 -08:00
David Harris
f2cf09dd76 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-18 16:14:42 -08:00
David Harris
b996598b37 CoreMark testing 2021-11-18 16:14:25 -08:00
slmnemo
870549c01a Removed .* from hazard hzu(.*). 2021-11-17 14:21:23 -08:00
slmnemo
a98dcd11ee Removed .* from hazard hzu(.*) in wallypipelinedhart.sv. 2021-11-17 14:08:08 -08:00
slmnemo
fed613dc72 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-17 13:38:51 -08:00
slmnemo
f4380faa4e removed .* from muldiv.sv (REAL) 2021-11-17 13:37:50 -08:00
David Harris
b49c419d0b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-17 13:28:33 -08:00
Noah Limpert
0ccc7d5fe8 ieu variable naming changed for clarity 2021-11-17 13:24:28 -08:00
slmnemo
9fb26d5a61 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-17 13:23:20 -08:00
slmnemo
573f8b0c42 Removed .*s from muldiv.sv 2021-11-17 13:23:12 -08:00
Noah Limpert
ed2285b8e7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-17 13:04:33 -08:00
Noah Limpert
832b23b8a4 Updated IFU variable naming for clarity 2021-11-17 12:39:05 -08:00
Kevin Kim
d4e9376854 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-17 12:18:25 -08:00
Kevin Kim
34b3cc1c8d root level makefile added 2021-11-17 12:17:56 -08:00
Kip Macsai-Goren
3f76549a7d renamed presrc to forwardedSrc, replaced SrcAE and SrcBE with Forwarded src in the muldiv 2021-11-17 10:53:17 -08:00
Ross Thompson
3b8bdc7b2d Created separate memory interface for the ddr4 fpga memory from the soc internal memory dtim. 2021-11-17 12:47:19 -06:00
Ross Thompson
11a21899d5 Fixed uart by reversing the bit order on transmit. 
Set prescale to 0.
 2021-11-17 10:32:41 -06:00
Skylar Litz
e35faa9b8a fixed interrupt timing bug 2021-11-16 16:46:17 -08:00
David Harris
5a521e28ee Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-16 12:30:55 -08:00
bbracker
23bd24323b get current privilege level from GDB for checkpoints 2021-11-15 14:49:00 -08:00
Ross Thompson
4af7a27d87 Have linux booting. Not sure about uart, but uart is now part of the ILA and I can see TX changing. 2021-11-12 17:37:07 -06:00
Ross Thompson
b8572d6a2a Changed several things. 
Removed the need to use async flip flops in SDC.
Added arrs, a synchronizer for reset.
I think this works with the real FPGA hardware.
The last build did not include this arrs but it worked.
 2021-11-12 11:13:50 -06:00
Skylar Litz
99a15e7897 fix timing of delayed interrupt 2021-11-11 09:35:51 -08:00
David Harris
f96152fa31 bringing Coremark back to life 2021-11-10 12:43:31 -08:00
Kevin Kim
a7684f1b59 Makefile added in regression directory: 
-cd's into imperas then runs make commands, finally running the tvLinker script
 2021-11-09 10:55:48 -08:00
bbracker
1597e0dac6 increase expectations for buildroot and timeout count 2021-11-06 14:57:29 -07:00
bbracker
24d3244cfe checkpoint MIDELEG support 2021-11-06 03:44:23 -07:00
bbracker
1d3d7cbe1e fix merge conflict 2021-11-05 23:42:15 -07:00
bbracker
3077769cbd checkpoints now use binary ram files 2021-11-05 22:37:05 -07:00
Kevin
b34569c358 changed code aligner to run recursively on a root directory 
-only runs the aligner on .sv files
-runs recursively on sub-directories
 2021-11-03 10:49:34 -07:00
bbracker
e4cf044932 fix testbench interrupt timing 2021-11-02 21:19:12 -07:00
bbracker
8563c0f016 linux testgen refactor 2021-11-01 14:09:49 -07:00
David Harris
910957704b Add3d wally32i test 2021-11-01 13:17:49 -07:00
David Harris
4b57af9cff PIPELINE test running 2021-11-01 12:44:35 -07:00
David Harris
c306884e2c Adding custom Wally test infrastructure 2021-11-01 08:48:46 -07:00
bbracker
38d26e857b fix buildroot graphical sim 2021-10-31 18:33:43 -07:00
David Harris
e9244e7a85 Fixed exe2memfile parsing of weird line in arch64d test 2021-10-30 07:26:18 -07:00
David Harris
f35b31f166 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-29 22:32:08 -07:00
David Harris
717f9d48e9 tesgen cleanup, added riscv-arch-test D tests 2021-10-29 22:31:48 -07:00
David Harris
f7acd31bcb rearranging testgen 2021-10-29 22:28:37 -07:00
Ross Thompson
8aad95366d Fixed the 4 way set associative pseudo LRU replacement policy. 2021-10-29 12:46:02 -05:00
Ross Thompson
f61fcd25a9 Possible fix for the incorrect behavior of the pseudo LRU replacement policy for 4 ways set associative caches. 2021-10-29 11:03:37 -05:00
Ross Thompson
54c714d222 Applied batch from fpga branch which fixes the dcache fence bug. The should cause the dcache to flush all dirty cache lines to main memory. The bug caused the dirty reset to clear each way for a particular line. 2021-10-28 11:07:18 -05:00
bbracker
fe2bf13720 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-27 14:40:31 -07:00
bbracker
d14fa074ec checkpoint generator off-by-one error fix 2021-10-27 14:10:29 -07:00
Noah Limpert
21ea270fe2 Have replaced .* with signal names in ifu 2021-10-27 13:45:37 -07:00
koooo142857
0a33b0904d aligned all files in ifu folder 2021-10-27 12:43:55 -07:00
David Harris
e62b57e2c2 commented out some failing FPU tests 2021-10-27 11:27:34 -07:00
David Harris
9cfb8deaab Fixed FResultSelM to select proper flags 2021-10-27 11:02:42 -07:00
David Harris
31a2346c37 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-27 10:37:46 -07:00
David Harris
0421b7af56 Changes for floating point sims 2021-10-27 10:37:35 -07:00
Ross Thompson
fed8882aec Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-27 09:59:55 -05:00
Ross Thompson
d98baf90a3 Replaced async reset flip flops with sync reset flip flops in cache and bpread. 2021-10-27 09:57:11 -05:00
Ross Thompson
0817ef20f1 Linux now boots fpga. 2021-10-26 16:49:16 -05:00
bbracker
52529db40b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-26 12:43:48 -07:00
bbracker
1409dc48a8 bugfix argument passing to GDB script; remove outdated GDB script 2021-10-26 12:43:42 -07:00
David Harris
f793dd7a5e removed unused signal from wave.do 2021-10-26 09:02:22 -07:00
David Harris
7d516c65e7 commented out nonworking tests 2021-10-26 08:56:49 -07:00
David Harris
ca700610f8 removed referenc outputs 2021-10-26 08:51:49 -07:00
David Harris
1a6fb2fad9 Forgot to save cacheway merge 2021-10-26 08:38:13 -07:00
David Harris
79c1395967 merging changes 2021-10-26 08:34:36 -07:00
David Harris
44de52a05a Synchronous reset in non-flop blocks 2021-10-26 08:30:35 -07:00
Ross Thompson
09b3549efd Fixed another critical path in the caches. 2021-10-25 22:05:11 -05:00
Ross Thompson
cb7015a690 Fixed the timing issue in the cache replacement polcy. 2021-10-25 18:00:23 -05:00
Ross Thompson
6c92d3267f Fixed bug with the changes to sram1rw. 2021-10-25 16:11:41 -05:00
Ross Thompson
c963ea1a64 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-25 15:36:21 -05:00
Ross Thompson
694b3fbb6f Possible fix for critical path timing in caches. 2021-10-25 15:33:33 -05:00
bbracker
f39a509b5b adapt testbench linux to use reset_ext 2021-10-25 13:26:44 -07:00
bbracker
f50787203f copy / link to checkpoint 8500000 dir 2021-10-25 13:24:02 -07:00
Ross Thompson
2f4ee26b60 Fixed issue with dtim (fpga) external abhlite select not triggering. 
Setup the bootloader (bios.s) to copy 127MB and blink LEDs for 5 seconds with 1 second period.
 2021-10-25 14:51:54 -05:00
bbracker
2c9c9328a9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-25 12:25:37 -07:00
bbracker
c61cbf9618 change CHECKPOINT to be a parameter (not a macro) so that do scripts can control it; clean up checkpoint initialization macros 2021-10-25 12:25:32 -07:00
Ross Thompson
f7583d0e0d Updated uncore to use sdc. 
Fixed bug with fence instruction not correctly clearing dirty bits in d cache.
 2021-10-25 14:07:44 -05:00
David Harris
14e6d2c576 Converted flops to synchronous reset now that reset signal is synchronized 2021-10-25 11:49:20 -07:00
David Harris
47124f36c8 Added synchronizer to reset 2021-10-25 10:05:41 -07:00
bbracker
b51e4d504b some linux testbench cleanup 2021-10-25 10:04:30 -07:00
Ross Thompson
ebef47b1c9 Modified the cache's sram model so if it used to synthesize flip flops it terminates the read critical path at the address's input rather than the output read data. 2021-10-24 21:21:49 -05:00
bbracker
d348ebffda checkpoint initialization bugfix 2021-10-24 18:39:51 -07:00
bbracker
9423b90780 switch linux graphical sim over to Ross's waves 2021-10-24 18:39:23 -07:00
bbracker
9cdbd9a0bf remove unused scripts 2021-10-24 15:19:03 -07:00
bbracker
4100ed9a7a update debugger script to new style 2021-10-24 15:18:44 -07:00