David Harris
4ffa5e7b0a
Coverage improvements
2024-01-22 09:49:24 -08:00
Jordan Carlin
4936496bb9
fix sfence.inval.ir and sret coverage from previous PR
2024-01-22 08:58:31 -08:00
David Harris
171430a695
FPU and PMP tests
2024-01-21 14:41:22 -08:00
David Harris
ff055c404c
fpu coverage improvements
2024-01-21 13:17:56 -08:00
David Harris
69218b4b86
Coverage improvements
2024-01-21 10:03:07 -08:00
David Harris
9260d3c424
Add Zfh support to imperas.ic, use Zicond in riscof now that it is fixed in riscv-arch-test
2024-01-18 22:46:07 -08:00
David Harris
13de147c7e
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-01-18 22:12:07 -08:00
David Harris
17c9be7695
Cleanup typos, remove Zicond from riscof until it is working
2024-01-18 21:36:52 -08:00
Jordan Carlin
82d9467eea
Add coverage of FIOM in different privelege modes
2024-01-18 19:29:16 -08:00
Jordan Carlin
12b2baff82
add coverage of sfence.inval.ir instruction and fix sret coverage
2024-01-18 17:33:59 -08:00
naichewa
8b60992e72
fixed SPI tests failing when no icache
2024-01-17 14:38:11 -08:00
David Harris
f8c88a398a
Coverage improvements
2024-01-15 07:16:41 -08:00
Jordan Carlin
51f670c821
Merge branch 'openhwgroup:main' into main
2024-01-12 19:43:01 -08:00
Jordan Carlin
6c797570fa
Add coverage for all Zcb instructions
2024-01-12 19:10:13 -08:00
Rose Thompson
0b2af0c99a
Modifed the sv39 tests so they work with just 128MiB physical memory.
2024-01-12 20:00:21 -06:00
Rose Thompson
e6a2595936
Modified sv48 svadu test to work with 128MB rather than 2GB physical memory.
2024-01-12 11:05:06 -06:00
David Harris
9eb6d9c8b8
Added Zicond support
2024-01-11 07:37:15 -08:00
David Harris
ba7e017bd9
Added Zcb c.lbu coverage test
2024-01-10 10:01:46 -08:00
David Harris
d36b6e919a
Fixed missing Zba ISA string from spike_rv64gc_isa.yaml for RISCOF
2024-01-09 10:00:06 -08:00
David Harris
caedab679a
Rewrote testbench to count signature entries rather than looking for x; this will facilitate Verilator which does not use x
2024-01-07 07:14:12 -08:00
David Harris
0781cd4a44
Improved tlbcontrol to fault on R=0,W=1; fixed more coverage testsin tlbmisc.S; changed integer type to try to speed up CoreMark; comments in Verilate
2024-01-05 22:45:15 -08:00
David Harris
ed623f1a71
Fixed unsupported riscof YAML string; preparing for Verilator -G testcase
2024-01-05 20:06:21 -08:00
David Harris
680a014876
Finished LSU tlbcontrol coverage tests
2024-01-02 10:16:20 -08:00
David Harris
d229dc06ee
Coverage improvements; remove incorrect logic checking NAPOT nonleaf PTE
2024-01-02 00:35:17 -08:00
David Harris
52b6d1d163
restored tlbNAPOT coverage tests
2023-12-31 09:55:58 -08:00
David Harris
b025cd8a0d
Updated tlbNAPOT to test instructions as well
2023-12-20 23:01:35 -08:00
David Harris
9ced88c55c
Fixed tlbNAPOT test to run and makefile to gather coverage stats
2023-12-20 21:45:14 -08:00
David Harris
d130a78616
Updated to current version of toolchain and prepare to be able to compile Zcb and Zicboz when supported
2023-12-20 16:29:03 -08:00
David Harris
0ff049db86
Removed unused tests from wally-riscv-arch-test
2023-12-20 13:34:12 -08:00
David Harris
8552369687
Merged PR538, delete unused tests
2023-12-20 13:30:31 -08:00
Rose Thompson
70d0169019
All regression tests which matter are running!
2023-12-20 14:57:52 -06:00
Rose Thompson
1b59182d59
Updated tests with ending label.
2023-12-20 14:55:37 -06:00
Rose Thompson
49b1b7c7f9
Fixed the last uninitialized memory issue in the priv tests.
2023-12-19 16:51:56 -06:00
Rose Thompson
b04ad23c33
Fixed bugs in the wally64periph signature.
2023-12-19 16:16:59 -06:00
Rose Thompson
726efee1e2
Fixed bugs in the cbom test.
2023-12-19 15:53:48 -06:00
Rose Thompson
418ae0decc
Fixed some regression tests with David's help.
2023-12-19 14:18:21 -06:00
David Harris
a138ef37b1
Switched to using riscv-arch-test rv32e_m suite. Need to rename it from rv32e_unratified (PR pending)
2023-12-15 19:26:50 -08:00
David Harris
38f4d9baf8
Use riscv-arch-test arch32e instead of outdated wally-riscv-arch-test wally32e
2023-12-15 05:05:53 -08:00
David Harris
29f57958a9
Fixed WALLY-lrsc in ImperasDV by setting reservation set size to native word size and adjusting imperas.ic lr_sc_grain=8 to match
2023-12-14 15:32:36 -08:00
David Harris
166c98b6f6
Fixed issue 526 about WALLY-mmu-sv39-svadu-svnapot-svpbmt not checking ppn for NAPOT pages. Improved test case to check normal and malformed ppn
2023-12-13 19:43:17 -08:00
David Harris
6c017141c5
Renamed HADE to ADUE for Svadu
2023-12-13 11:49:04 -08:00
David Harris
0f0b4b0c1c
Added make wally-riscv-arch-test to tests/riscof to only build custom tests
2023-12-06 07:19:12 -08:00
David Harris
2b2016271a
repo cleanup and start to add CMO tests
2023-11-20 23:41:36 -08:00
Rose Thompson
540d8d930d
Cleanup.
...
Linux makefile
wally tracer. probably reduce some complexity here.
2023-11-13 14:04:43 -06:00
Rose Thompson
9dfe421c55
Yay! Zicclsm passes my regression test now.
2023-11-10 18:28:51 -06:00
Rose Thompson
c0e02ae190
Found another bug in the RTL's Zicclsm alignment.
2023-11-10 18:26:55 -06:00
Rose Thompson
02ab9fe99c
Fixed all the bugs associated with the signature and the store side of misaligned access. Load misaligned is still causing some issues.
2023-11-10 17:58:42 -06:00
Rose Thompson
bd866e1025
Fixed some more bugs in the Zicclsm signature.
2023-11-10 17:36:10 -06:00
Rose Thompson
efecb0c346
Fixed bug in the Zicclsm test.
2023-11-10 17:34:23 -06:00
Rose Thompson
ada354f443
Fixed bug in the misaligned access test.
2023-11-10 17:02:15 -06:00
Rose Thompson
b74bfbeefd
Merge branch 'main' into Zicclsm
2023-11-10 16:15:32 -06:00
naichewa
d67badfc60
fix hardware interlock, hold mode deassert
2023-11-08 15:20:51 -08:00
naichewa
a5837eb62c
fifo fixes and edge case testing
2023-11-07 17:59:46 -08:00
naichewa
4651b807ed
added test cases
2023-11-02 15:43:08 -07:00
Rose Thompson
0a4ed5515b
Merge branch 'main' into Zicclsm
2023-11-02 12:55:51 -05:00
Rose Thompson
afa1d85e3b
Doesn't yet fully work.
...
Thomas is going to finish debugging while I'm on the RISCV summit next week.
2023-11-02 12:07:42 -05:00
Rose Thompson
7ba891f607
Progress. I think the remaining bugs are in the regression test's signature.
2023-11-01 17:51:48 -05:00
naichewa
9aa8a7af3e
comments, more test cases
2023-11-01 01:26:34 -07:00
Rose Thompson
5660eff57d
Working through issues with the psill logic.
2023-10-31 18:50:13 -05:00
Rose Thompson
4984b3935f
Progress
2023-10-31 14:50:33 -05:00
Rose Thompson
5ca428d6a8
Fixed bugs in misaligned test.
2023-10-31 12:49:35 -05:00
Rose Thompson
c061440141
First stab at the misaligned test.
2023-10-31 12:30:10 -05:00
naichewa
7dd3f24d6c
Merge branch 'main' into spi
2023-10-30 17:01:41 -07:00
naichewa
2330f4ee63
hardware interlock
2023-10-30 17:00:20 -07:00
Rose Thompson
2241976d29
Updated mmu to not generate trap on cacheable misaligned access when supported.
...
Updated tests with David's help.
2023-10-30 18:26:11 -05:00
David Harris
f6a7f707bd
Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder.
2023-10-30 09:56:17 -07:00
Rose Thompson
0fd5b3b2ce
Updated comments in the cboz tests.
2023-10-20 15:15:47 -05:00
Rose Thompson
5a4028064a
Updated comments for the cbom tests.
2023-10-20 15:13:52 -05:00
naichewa
0ff9ce527d
Merge branch 'main' into spi
2023-10-16 22:59:50 -07:00
David Harris
ac4216b43d
Incorporated new AMO tests from riscv-arch-test
2023-10-16 10:25:45 -07:00
David Harris
6245748ed7
Added CSR permission tests for mconfigptr, menvcfg, mseccfg, etc.
2023-10-15 15:31:03 -07:00
David Harris
b4891d88db
Added WALLY minfo test for rv32
2023-10-15 06:48:22 -07:00
David Harris
434d6b2c5c
minfo test working again with mconfigptr for RV64
2023-10-15 06:41:52 -07:00
naichewa
aa5abfc8e8
always working after reg bit swizzle changes
2023-10-13 14:22:32 -07:00
naichewa
f231c3d3a3
correct delay0, fmt register test entries
2023-10-12 15:13:23 -07:00
naichewa
d5d4f9d044
transferred spi changes in ECA-authorized commit
2023-10-12 13:36:57 -07:00
David Harris
d526d28804
Added MENVCFG.HADE bit and updated SVADU to depend on this bit
2023-10-04 09:34:28 -07:00
Ross Thompson
9ff3642c6c
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-09-05 11:12:00 -05:00
David Harris
9747d122d2
tlbNAPOT hangs due to PBMT making instruction memory uncacheable, and spill logic not working there. Fixed TLBLRU to update recently used on TLBHit rather than CAMHit. Moved coverage exclusions to proper line in pmachecker
2023-09-02 12:56:36 -07:00
David Harris
e75ceb044f
Improved tlb and controller coverage; fixed exclusions on broken lines
2023-08-31 00:27:47 -07:00
David Harris
1642ad2bad
Improved NAPOT test coverage
2023-08-30 21:04:36 -07:00
Ross Thompson
12c3c98824
Extended the CBOM test to cover a 4 way set associative cache with 4KiB ways.
2023-08-30 11:29:44 -05:00
David Harris
91429f3f02
Initial TLB NAPOT tests
2023-08-29 12:39:24 -07:00
David Harris
8d3ff59673
Completed basic tests of svnapot and svpbmt
2023-08-28 06:57:35 -07:00
David Harris
0e16203cd8
Merge pull request #393 from ross144/main
...
Implemented and tested CBOZ instruction
2023-08-24 19:17:38 -07:00
David Harris
c45fbe1ffe
Merge pull request #394 from harshinisrinath1001/main
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Improved testing of csri with priv.S!
2023-08-24 19:16:50 -07:00
harshinisrinath
c9112ff18d
Improved testing of csri with priv.S
2023-08-24 18:39:15 -07:00
Ross Thompson
cd3349bd26
Added rv32 cboz test.
2023-08-24 17:02:53 -05:00
Ross Thompson
914b6f9734
Now have CBOZ instructions working!
2023-08-24 16:47:35 -05:00
Ross Thompson
7d51690b7c
Oups forgot to include the 32-bit cbom test in previous commit.
2023-08-24 09:04:41 -05:00
David Harris
d801916d97
Merge pull request #383 from ross144/main
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Adds Zicbom support for D-cache only. I-cache not yet supported. Tests 32 and 64 bit versions. Please rebuild regressions wally32 and wally64. To save rebuild time edit lines 11-12 of tests/riscof/Makefile
2023-08-21 13:32:00 -07:00
David Harris
409abbf443
Merge pull request #381 from harshinisrinath1001/main
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Tried to improve coverage of CSRI with priv.S
2023-08-21 13:28:39 -07:00
Ross Thompson
310b700550
Have a working 32 bit cbom test!
2023-08-21 13:46:09 -05:00
Ross Thompson
d4c6ba627d
Working CBO tests for 64 bit!
2023-08-21 12:55:07 -05:00
Ross Thompson
5ed096e4bc
Made a bunch of progress towards getting cbo instructions tested.
2023-08-21 11:46:21 -05:00
harshinisrinath
3d3d15077b
cleared stimer interrupt
2023-08-20 15:42:27 -07:00
harshinisrinath
fdb7abec06
tried to improve testing of csri in privileged module
2023-08-20 15:40:02 -07:00
David Harris
2738423441
Improved CSRU coverage with priv.S
2023-08-20 12:49:31 -07:00
harshinisrinath
7494ce06eb
wrote testcase to write into FSCR
2023-08-20 12:10:08 -07:00
Ross Thompson
05d590b0b9
Fixed issue when with flush miss.
2023-08-18 16:36:13 -05:00
