bbracker
2ffdbdf6d2
condense testbench code; debug_level of 0 means don't check at all
2021-09-27 03:03:11 -04:00
Ross Thompson
f2c1ca4bd5
added support to due partial fpga simulation.
2021-09-26 15:00:00 -05:00
Ross Thompson
6ac96db20b
Merge branch 'main' into fpga
2021-09-26 13:22:53 -05:00
Ross Thompson
5bdd6a9d0c
Almost done writting driver for flash card reader.
2021-09-25 19:05:07 -05:00
Ross Thompson
3a15cc7872
We now have a rough sdc read routine.
2021-09-25 17:51:38 -05:00
Ross Thompson
232d4a554f
Have program which checks for sdc init and issues read, but read done is
...
not correctly being read back by the software. The error is in how the
sdc indicates busy.
2021-09-24 15:53:38 -05:00
Ross Thompson
0f87f68b9d
Added either the sdModel or constant driver for the SDC ports in all test benches.
2021-09-24 12:31:51 -05:00
Ross Thompson
0a33f5fa46
setup so the sdc does not need to load a model in the imperas test bench.
2021-09-24 11:30:52 -05:00
Ross Thompson
78028947bf
Updated Imperas test bench to work with the SDC reader.
2021-09-24 11:22:54 -05:00
bbracker
441759b81c
switch testbench-linux's interrupts from xcause to mip and improve warning messages
2021-09-22 12:33:11 -04:00
bbracker
b1be8f4858
fix regression
2021-09-15 17:30:59 -04:00
David Harris
e32ab128e9
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-13 12:41:07 -04:00
David Harris
654f3d1940
Fixed MTVAL contents during breakpoint. Now all riscv-arch-test vectors pass in rv32 and rv64
2021-09-13 12:40:40 -04:00
Ross Thompson
d4c87d17b2
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-09-13 09:41:34 -05:00
David Harris
1847198da9
Cleaned up wally-arch test scripts
2021-09-13 00:02:32 -04:00
Ross Thompson
144003cb41
FPGA test bench and test program.
2021-09-12 20:41:54 -05:00
David Harris
cb624fe679
Lint cleaning, riscv-arch-test testing
2021-09-09 11:05:12 -04:00
David Harris
a31828e925
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-08 16:00:12 -04:00
David Harris
30e2ec3987
Added testbench-arch for riscv-arch-test suite
2021-09-08 15:59:40 -04:00
Ross Thompson
6606eea27e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-09-08 12:47:03 -05:00
bbracker
5e9a39e755
fixed bug where M mode was sensitive to S mode traps
2021-09-07 19:14:39 -04:00
bbracker
b3f00f2682
make testbench successfully deactivate TimerIntM so as to create a nice pulse
2021-09-07 15:36:47 -04:00
bbracker
28fed18421
No longer forcing CSRReadValM because that can feedback to corrupt some CSRs
2021-09-06 22:59:54 -04:00
bbracker
a13b561759
modified testbench to not allow Wally to generate its own interrupts (because of fundamental interrupt imprecision limitations)
2021-09-04 19:49:26 -04:00
Ross Thompson
b3849d8abb
Moved data path logic from icacheCntrl to icache.
2021-08-26 10:58:19 -05:00
Ross Thompson
c48556836b
Removed generate around the dcache memories.
2021-08-25 13:27:26 -05:00
Ross Thompson
b7972eafeb
Added function tracking to linux test bench.
2021-08-24 11:08:46 -05:00
Ross Thompson
97653e1aea
Wally previously was overcounting retired instructions when they were flushed.
...
InstrValidM was used to control when the counter was updated. However this is
not suppress the counter when the instruction is flushed in the M stage.
2021-08-23 12:24:03 -05:00
Ross Thompson
b6e2710f5d
Confirmed David's changes to the interrupt code.
...
When a timer interrupt occurs it should be routed to the machine interrupt
pending MTIP even if MIDELEG[5] = 1 when the current privilege mode is
Machine. This is true for all the interrupts. The interrupt should not be
masked even though it is delegated to a lower privilege. Since the CPU
is currently in machine mode the interrupt must be taken if MIE.
Additionally added a new qemu script which pipes together all the parsing and
post processing scripts to produce the singular all.txt trace without the
massivie intermediate files.
2021-08-22 21:36:31 -05:00
Ross Thompson
4eca94268c
Added logic to linux test bench to not stop simulation on csr write faults.
2021-08-15 11:13:32 -05:00
Ross Thompson
4f3f26c5cb
Switched ExceptionM to dcache to be just exceptions.
...
Added test bench logic to hold forces until the W stage is unstalled.
2021-08-13 15:53:50 -05:00
Ross Thompson
492b6f0ea4
Fixed bugs with CSR checking. The parsing algorithm was messing up the token order after the CSR token.
2021-08-13 14:53:43 -05:00
Ross Thompson
a1c26a16d6
Cleaned up the linux testbench by removing old code and signals.
...
Added back in the csr checking logic.
Added code to force timer, external, and software interrupts by using the expected
values from qemu's (m/s)cause registers.
Still need to prevent wally's timer interrupt.
2021-08-13 14:39:05 -05:00
Ross Thompson
3b327c949f
Minor cleanup of the linux test bench.
2021-08-12 11:14:55 -05:00
Ross Thompson
467e24c05c
Fixed another bug with the atomic instrucitons implemention in the dcache.
2021-08-08 22:50:31 -05:00
Ross Thompson
25533bdc49
Fixed the AMO dcache bug. The subword write needs to occur before the AMO logic.
...
Fixed logic for trace update in the M and W stages. The M stage should not update if there
is an instruction fault.
2021-08-08 00:28:18 -05:00
Ross Thompson
fda9985382
Finally past the CLINT issues.
2021-08-06 16:41:34 -05:00
Ross Thompson
839822d3b1
Now past the CLINT issues.
2021-08-06 16:16:39 -05:00
Ross Thompson
e1319a2fbe
Partial conversion of the linux trace checking to read in the file in the Memory Stage so it is possible to overwrite registers, memory, and interrupts.
2021-08-06 16:06:50 -05:00
Ross Thompson
d430659983
fixed the read timer issue but we still have problems with interrupts and i/o devices.
2021-08-06 10:16:06 -05:00
Ross Thompson
722d298c35
Fixed issue with desync of PCW and ExpectedPCW in linux test bench. The ERROR macro had a 10 ns delay which caused the trace to skip 1 instruction.
2021-08-05 16:49:03 -05:00
Ross Thompson
245e7014b3
Added some comments to linux testbench.
2021-07-30 17:57:03 -05:00
Ross Thompson
cd8a66353c
Patched up changes for wally-pipelined.do and wally-buildroot.do to support moved common testbench files.
2021-07-30 14:24:50 -05:00
Ross Thompson
ef66cdeecf
Moved the test bench modules to a common directory.
2021-07-30 14:16:14 -05:00
Ross Thompson
b9f8c25280
Created new linux test bench and parsing scripts.
2021-07-29 20:26:50 -05:00
Kip Macsai-Goren
8823339aef
added tests for 64/32 bit pma/pmp checker. They compile, but skip OVPsim simulation. They DO NOT pass regression yet
2021-07-23 16:02:42 -04:00
Kip Macsai-Goren
0653630d29
added sfence to legal instructions, zeroed out rom file to populate for tests
2021-07-23 15:55:08 -04:00
Kip Macsai-Goren
f02d52ce50
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-23 15:16:01 -04:00
bbracker
71ef87bc55
testbench workaround for QEMU's SSTATUS XLEN bits
2021-07-23 14:00:44 -04:00
Kip Macsai-Goren
ee1eef3620
include SFENCE.VMA in legal instructions
2021-07-22 20:24:24 -04:00
David Harris
625d925369
Partial work on Unpacking exponents to larger word size. FCVT and FMA are presently broken.
2021-07-22 14:18:27 -04:00
bbracker
70ef670da1
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-21 20:07:03 -04:00
bbracker
3c6a1f8824
replace physical address checking with virtual address checking because address translator is broken
2021-07-21 19:47:13 -04:00
Katherine Parry
59f79722ab
FDIV and FSQRT work
2021-07-21 14:08:14 -04:00
Katherine Parry
61f81bb76e
FMA parameterized
2021-07-20 22:04:21 -04:00
bbracker
d6c93a50aa
fix PC checking during InstrPageFault; fix order of S-mode CSR checking; rename peripheral scopes to not be genblk
2021-07-20 17:55:44 -04:00
bbracker
b5ceb6f7c3
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-20 15:04:13 -04:00
bbracker
945c8d496f
commented out old hack that used hardcoded addresses
2021-07-20 15:03:55 -04:00
David Harris
62b3673027
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-20 14:46:58 -04:00
David Harris
20744883df
flag for optional boottim
2021-07-20 14:46:37 -04:00
bbracker
7694342d4e
ignore mhpmcounters because QEMU doesn't implement them
2021-07-20 13:37:52 -04:00
bbracker
761300afcd
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-20 12:08:46 -04:00
David Harris
c117356432
Parameterized I$/D$ configurations and added sanity check assertions in testbench
2021-07-20 08:57:13 -04:00
bbracker
c9775de3b2
testbench hack to ignore MTVAL for illegal instr faults; testbench upgrade to not check PCW for illegal instr faults; testbench hack to not check speculative instrs following an MRET (it seems MRET has 1 stage more latency than a branch instr)
2021-07-20 05:40:39 -04:00
bbracker
5347a58192
major fixes to CSR checking
2021-07-20 00:22:07 -04:00
bbracker
aeaf4a31f0
MemRWM shouldn't factor into PCD checking
2021-07-19 18:03:30 -04:00
bbracker
5911029d2b
make testbench ignore MIP because of timing imprecision and because QEMU maybe isn't getting MTIP right anyways
2021-07-19 17:11:42 -04:00
bbracker
009e9d97bf
adapt testbench to removal of ReadDataWEn signal
2021-07-19 15:42:14 -04:00
bbracker
02de6014b2
adapt testbench to removal of signal
2021-07-19 15:41:50 -04:00
bbracker
77b690faf0
make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset
2021-07-19 15:13:03 -04:00
Katherine Parry
8d101548f1
FDIV and FSQRT passes when simulating in modelsim
2021-07-18 23:00:04 -04:00
bbracker
f4f3ef0307
linux testbench progress
2021-07-18 18:47:40 -04:00
Katherine Parry
3527620c0b
fdivsqrt inegrated, but not completley working
2021-07-18 14:03:37 -04:00
Ross Thompson
a0017e39e2
Fixed bug with rv32a/WALLY-LRSC test in imperas. Minor issue.
2021-07-17 21:02:24 -05:00
David Harris
c29a2ff8df
Started atomics
2021-07-17 21:11:41 -04:00
bbracker
6feb95c779
swapped out linux testbench signal names
2021-07-17 14:48:12 -04:00
David Harris
9741b01465
hptw: minor cleanup
2021-07-17 13:40:12 -04:00
David Harris
37cc2ca30f
hptw: factored pregen
2021-07-17 11:11:10 -04:00
David Harris
622a14cbdd
Removed more unused signals from ahblite
2021-07-17 02:21:54 -04:00
Kip Macsai-Goren
3d14d573a0
included virtual memory tests in testbench
2021-07-16 17:57:24 -04:00
Ross Thompson
965f34d78f
Added guide for Ben to do linux conversion.
2021-07-16 15:04:30 -05:00
Ross Thompson
abce241f68
Also changed the shadow ram's dcache copy widths.
...
Merge branch 'dcache' into main
2021-07-16 14:21:09 -05:00
Ross Thompson
96aa106852
Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault.
2021-07-15 11:56:35 -05:00
Ross Thompson
4549a9f1c9
Merge branch 'main' into dcache
2021-07-15 11:55:20 -05:00
Ross Thompson
c39a228266
Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits.
2021-07-15 11:00:42 -05:00
Ross Thompson
f234875779
dcache STATE_CPU_BUSY needs to assert CommittedM. This is required to ensure a completed memory operation is not bound to an interrupt. ie. MEPC should not be PCM when committed.
2021-07-14 23:08:07 -05:00
Ross Thompson
6163629204
Finally have the ptw correctly walking through the dcache to update the itlb.
...
Still not working fully.
2021-07-14 22:26:07 -05:00
Katherine Parry
701ea38964
Fixed lint warning
2021-07-14 21:24:48 -04:00
Ross Thompson
d3a1a2c90a
Fixed d cache not honoring StallW for uncache writes and reads.
2021-07-14 17:23:28 -05:00
Ross Thompson
771c7ff130
Routed CommittedM and PendingInterruptM through the lsu arb.
2021-07-14 16:18:09 -05:00
Ross Thompson
278bbfbe3c
Partially working changes to support uncached memory access. Not sure what CommitedM is.
2021-07-13 17:24:59 -05:00
Katherine Parry
acdd2e4504
Fixed writting MStatus FS bits
2021-07-13 13:20:30 -04:00
Ross Thompson
d3ffbe0e5d
Modularized the shadow memory to reduce performance hit.
2021-07-13 10:55:57 -05:00
Ross Thompson
17dc488010
Got the shadow ram cache flush working.
2021-07-13 10:03:47 -05:00
Ross Thompson
9fe6190763
Team work on solving the dcache data inconsistency problem.
2021-07-12 23:46:32 -05:00
Ross Thompson
6b42b93886
Now updates the dtim with the dirty data in the dcache.
...
Simulation is showing issues. It lookslike the cache is not
evicting the correct data.
2021-07-12 15:13:27 -05:00
Ross Thompson
8ca8b9075d
Progress towards the test bench flush.
2021-07-12 14:22:13 -05:00
Katherine Parry
0cc07fda1b
Almost all convert instructions pass Imperas tests
2021-07-11 18:06:33 -04:00
bbracker
0e708a72f3
more completely uncomment MMU tests to make sim wally work
2021-07-06 14:33:52 -04:00
Kip Macsai-Goren
770420b448
added new mmu tests to makefrag and commented out in the testbench
2021-07-05 10:54:30 -04:00
David Harris
e65fb5bb35
Added F_SUPPORTED flag to disable floating point unit when not in MISA
2021-07-05 10:30:46 -04:00
David Harris
c897bef8cd
Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
2021-07-04 01:19:38 -04:00
Ben Bracker
9709bd78e1
stop busybear from hanging
2021-07-02 17:22:09 -05:00
bbracker
9927f771cc
linux testbench now ignores HWRITE glitches caused by flush glitches
2021-06-25 09:28:52 -04:00
bbracker
2694a7a43f
made testbench-linux's PCDwrong be FlushD
2021-06-25 08:15:19 -04:00
Katherine Parry
bc8d660bc5
FPU forwarding reworked pt.1
2021-06-24 18:39:18 -04:00
bbracker
55cf205222
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-24 01:42:41 -04:00
bbracker
b84419ff4e
overhauled linux testbench and spoofed MTTIME interrupt
2021-06-24 01:42:35 -04:00
Katherine Parry
44af47608c
fpu clean-up
2021-06-23 16:42:40 -04:00
Katherine Parry
9eb6eb40bf
rv64f FLW passes imperas tests
2021-06-22 16:36:16 -04:00
David Harris
82515862e3
Commented out 100k tests to improve speed
2021-06-21 01:43:18 -04:00
David Harris
aef408af58
Reversed [0:...] with [...:0] in bus widths across the project
2021-06-21 01:17:08 -04:00
bbracker
5afad80432
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-20 22:29:40 -04:00
bbracker
665a67f442
linux actually uses FPU now!
2021-06-20 22:29:21 -04:00
Katherine Parry
26bad083ad
all rv64f instructions except convert, divide, square root, and FLD pass
2021-06-20 20:24:09 -04:00
bbracker
1f2a967e0f
read from MSTATUS workaround because QEMU has incorrect MSTATUS
2021-06-20 10:11:39 -04:00
bbracker
2611d214a6
testbench update b/c QEMU extends 32b CSRs to 64b
2021-06-20 09:24:19 -04:00
bbracker
9469367da3
make buildroot ignore SSTATUS because QEMU did not originally log it
2021-06-20 05:31:24 -04:00
bbracker
78f4703dc9
MSTATUS workaround
2021-06-20 04:48:09 -04:00
bbracker
927d99cf3b
workaround for ignoring MTIME
2021-06-20 02:26:39 -04:00
bbracker
3e32ba3684
make buildroot waves only turn on after a user-specified point
2021-06-20 00:39:30 -04:00
bbracker
f84a689c19
fixed PCtext error by using blocking assignments
2021-06-18 17:37:40 -04:00
bbracker
958f60c704
restore graphical buildroot sim
2021-06-18 11:58:16 -04:00
bbracker
8ae333a6b2
remove unused testbench-busybear.sv
2021-06-18 08:15:19 -04:00
David Harris
72d8d34e3c
allow all size memory access in CLINT; added underscore to peripheral address symbols
2021-06-18 08:05:50 -04:00
David Harris
e03912f64c
Cleaned up name of MTIME register in CSRC
2021-06-18 07:53:49 -04:00
bbracker
832e4fc7e3
making linux waveforms more useful
2021-06-17 08:37:37 -04:00
bbracker
e93e528aa1
changed parsedCSRs2] to parsedCSRs
2021-06-17 05:18:14 -04:00
David Harris
9dd3857c26
Fixed lint WIDTH errors
2021-06-09 20:58:20 -04:00
David Harris
cfe5c27946
Resized BOOT TIM to 1 KB
2021-06-08 14:04:32 -04:00
bbracker
17960a6484
Ah big ole merge! Passes sim-wally-batch and linting, so should be fine
2021-06-08 12:41:25 -04:00
bbracker
5026a42fac
* GPIO comprehensive testing
...
* MEPC more aware if M stage has actually committed
* UART interrupt testing progress
* UART added read IIR side effect of lowering THRE intr
2021-06-08 12:32:46 -04:00
Kip Macsai-Goren
46b2b19792
implemented simpler page mixers, cleaned up a bit
2021-06-07 18:32:34 -04:00
David Harris
b37bcc8e38
Continued merge
2021-06-07 12:49:47 -04:00
David Harris
1e67db2f0c
Second attept to commit refactoring config files
2021-06-07 12:37:46 -04:00
David Harris
95cc70295b
Merge difficulties
2021-06-07 09:50:23 -04:00
David Harris
8bbabb683d
Refactored configuration files and renamed testbench-busybear to testbench-linux
2021-06-07 09:46:52 -04:00
Katherine Parry
e4db6ea6f5
fixed lint warnings for fpu and lzd
2021-06-05 12:06:33 -04:00
Kip Macsai-Goren
b99b5f8e0e
moved privilege dfinitions into wally-constants, upgraded relevant includes
2021-06-04 17:55:07 -04:00
Katherine Parry
19116ed889
Double-precision FMA instructions
2021-06-04 14:00:11 -04:00
Kip Macsai-Goren
a84dd6dfc5
added tests for SV48 and translation off with vmem
2021-06-03 14:28:52 -04:00
James E. Stine
bccdd2c137
Updates to muldiv.sv for 32-bit div/rem
2021-06-01 15:31:07 -04:00
Ross Thompson
8f9680556f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-01 11:33:12 -05:00
Ross Thompson
5bc2a8b346
Now have global history working correctly.
2021-06-01 10:57:43 -05:00
James E. Stine
927aec34a2
Modify muldiv.sv to handle W instructions for 64-bits
2021-05-31 23:27:42 -04:00
bbracker
a45b61ede9
turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
2021-05-28 23:11:37 -04:00
Katherine Parry
0646e08609
classify unit created and passes imperas tests
2021-05-27 18:53:55 -04:00
Katherine Parry
65eca433b6
All compare instructions pass imperas tests
2021-05-27 15:23:28 -04:00
Katherine Parry
bd05de0dbb
FADD and FSUB imperas tests pass
2021-05-26 12:33:33 -04:00
Kip Macsai-Goren
ba134eb166
partially complete MSTATUS test of sd, xs, fs, mie, mpp, mpie, sie, spie bitfields
2021-05-24 20:59:26 -04:00
