bbracker 761300afcd Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main		2021-07-20 12:08:46 -04:00
..
function_radix.sv	Fixed memory size in configs for rv32ic and rv64ic.	2021-04-29 17:36:46 -05:00
testbench-coremark_bare.sv	Reversed [0:...] with [...:0] in bus widths across the project	2021-06-21 01:17:08 -04:00
testbench-coremark.sv	Reversed [0:...] with [...:0] in bus widths across the project	2021-06-21 01:17:08 -04:00
testbench-imperas.sv	Parameterized I$/D$ configurations and added sanity check assertions in testbench	2021-07-20 08:57:13 -04:00
testbench-linux.sv	testbench hack to ignore MTVAL for illegal instr faults; testbench upgrade to not check PCW for illegal instr faults; testbench hack to not check speculative instrs following an MRET (it seems MRET has 1 stage more latency than a branch instr)	2021-07-20 05:40:39 -04:00
testbench-privileged.sv	Reversed [0:...] with [...:0] in bus widths across the project	2021-06-21 01:17:08 -04:00