cvw/wally-pipelined/testbench
2021-07-15 11:56:35 -05:00
..
function_radix.sv Fixed memory size in configs for rv32ic and rv64ic. 2021-04-29 17:36:46 -05:00
testbench-coremark_bare.sv Reversed [0:...] with [...:0] in bus widths across the project 2021-06-21 01:17:08 -04:00
testbench-coremark.sv Reversed [0:...] with [...:0] in bus widths across the project 2021-06-21 01:17:08 -04:00
testbench-imperas.sv Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault. 2021-07-15 11:56:35 -05:00
testbench-linux.sv Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang. 2021-07-04 01:19:38 -04:00
testbench-privileged.sv Reversed [0:...] with [...:0] in bus widths across the project 2021-06-21 01:17:08 -04:00