Ross Thompson 25533bdc49 Fixed the AMO dcache bug. The subword write needs to occur before the AMO logic. ... Fixed logic for trace update in the M and W stages. The M stage should not update if there is an instruction fault.		2021-08-08 00:28:18 -05:00
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common	Moved the test bench modules to a common directory.	2021-07-30 14:16:14 -05:00
imperas-boottim.txt	added sfence to legal instructions, zeroed out rom file to populate for tests	2021-07-23 15:55:08 -04:00
testbench-coremark_bare.sv	Moved the test bench modules to a common directory.	2021-07-30 14:16:14 -05:00
testbench-coremark.sv	Moved the test bench modules to a common directory.	2021-07-30 14:16:14 -05:00
testbench-imperas.sv	Moved the test bench modules to a common directory.	2021-07-30 14:16:14 -05:00
testbench-linux.sv	Fixed the AMO dcache bug. The subword write needs to occur before the AMO logic.	2021-08-08 00:28:18 -05:00
testbench-privileged.sv	Moved the test bench modules to a common directory.	2021-07-30 14:16:14 -05:00