Ross Thompson 6b42b93886 Now updates the dtim with the dirty data in the dcache. ... Simulation is showing issues. It lookslike the cache is not evicting the correct data.		2021-07-12 15:13:27 -05:00
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function_radix.sv	Fixed memory size in configs for rv32ic and rv64ic.	2021-04-29 17:36:46 -05:00
testbench-coremark_bare.sv	Reversed [0:...] with [...:0] in bus widths across the project	2021-06-21 01:17:08 -04:00
testbench-coremark.sv	Reversed [0:...] with [...:0] in bus widths across the project	2021-06-21 01:17:08 -04:00
testbench-imperas.sv	Now updates the dtim with the dirty data in the dcache.	2021-07-12 15:13:27 -05:00
testbench-linux.sv	Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.	2021-07-04 01:19:38 -04:00
testbench-privileged.sv	Reversed [0:...] with [...:0] in bus widths across the project	2021-06-21 01:17:08 -04:00