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  • a3b5ae9742 Restore original order of tests Thomas Fleming 2021-05-03 23:50:21 -0400
  • ad40464557 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Thomas Fleming 2021-05-03 23:15:39 -0400
  • 803a69efe6 Enable mmu tests in testbench Thomas Fleming 2021-05-03 23:15:23 -0400
  • c0f054556c Fix bug with IllegalInstrFaultM not getting correct value Domenico Ottolia 2021-05-03 22:48:03 -0400
  • 2669a6a0db Run all tests Domenico Ottolia 2021-05-03 22:38:59 -0400
  • 4d70e22a6a Update cause tests to be longer Domenico Ottolia 2021-05-03 22:38:26 -0400
  • 997c9ad5c0 Add mtvec and stvec tests to testbench Domenico Ottolia 2021-05-03 22:19:50 -0400
  • 780ad3eaf4 working testbench-imperas Shriya Nadgauda 2021-05-03 22:16:58 -0400
  • c5a306426a finishing merge conflict changes Shriya Nadgauda 2021-05-03 22:15:05 -0400
  • b7159652f6 merge conflict fixes Shriya Nadgauda 2021-05-03 22:12:30 -0400
  • 968994c04a updated pipeline tests Shriya Nadgauda 2021-05-03 22:07:36 -0400
  • 0254ca7bf6 Adjust attributes in PMA checker Thomas Fleming 2021-05-03 21:58:32 -0400
  • b7056c85bd Get MMU tests working in OVPsim Thomas Fleming 2021-05-03 21:58:05 -0400
  • afd6153044 Rolled back fflush on uart. Use -syncio in Modelsim command line instead. David Harris 2021-05-03 20:04:44 -0400
  • 603c7712a9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-05-03 19:51:54 -0400
  • d07a7fd0f8 Flush uart print statements on \n David Harris 2021-05-03 19:51:51 -0400
  • a654b8a3d3 coremark update Elizabeth Hedenberg 2021-05-03 19:38:53 -0400
  • 93466a0b2a Flush uart print statements on \n David Harris 2021-05-03 19:41:37 -0400
  • e265aa4d41 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-05-03 19:37:56 -0400
  • 58ce0fbbcc Flush uart print statements on \n David Harris 2021-05-03 19:37:45 -0400
  • 2d1d929485 coremark print statment Elizabeth Hedenberg 2021-05-03 19:27:34 -0400
  • 2a33673e3c coremark updates Elizabeth Hedenberg 2021-04-28 14:21:53 -0400
  • b99fbc73f1 coremark update Elizabeth Hedenberg 2021-04-28 14:20:55 -0400
  • 7f5b8e63ed Coremark objump push Elizabeth Hedenberg 2021-04-28 14:16:18 -0400
  • 463ba1a2be coremark directory changes Elizabeth Hedenberg 2021-04-14 23:09:37 -0400
  • b66c7b81de Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-05-03 19:29:01 -0400
  • 233726e8d8 Flush uart print statements on \n David Harris 2021-05-03 19:25:28 -0400
  • baf29454f1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Ross Thompson 2021-05-03 16:57:36 -0500
  • 0f10d577d2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Domenico Ottolia 2021-05-03 17:56:05 -0400
  • 82b4d42f32 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Ross Thompson 2021-05-03 16:56:00 -0500
  • 7f38056879 fixed subtle typo in icache fsm. Was messing up hit spill hit. I believe the mibench qsort benchmark runs after this icache fix. Ross Thompson 2021-05-03 16:55:36 -0500
  • 5ab86a690b Fix bug that caused stvec to get the wrong value Domenico Ottolia 2021-05-03 17:54:57 -0400
  • ba1afec621 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Thomas Fleming 2021-05-03 17:38:13 -0400
  • eda5a267ee Implement PMP checker and revise PMA checker Thomas Fleming 2021-05-03 17:37:42 -0400
  • 8dce32fd22 Remove remnants of InstrReadC Thomas Fleming 2021-05-03 17:36:25 -0400
  • 7d509252a7 Add lint to regression Jarred Allen 2021-05-03 17:32:05 -0400
  • e145670b15 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Ross Thompson 2021-05-03 14:53:54 -0500
  • cdb602c9ce Removed combinational loops between icache and PMA checker. Ross Thompson 2021-05-03 14:51:25 -0500
  • 19a93345b5 Reduced icache to 1 port memory. Ross Thompson 2021-05-03 14:36:09 -0500
  • d7438929d4 Extended maximum signature length to 1M David Harris 2021-05-03 15:29:20 -0400
  • ff5a809c26 fpu warnings fixed/commented Katherine Parry 2021-05-03 19:17:09 +0000
  • cfe64e7c24 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Thomas Fleming 2021-05-03 14:02:19 -0400
  • a54c231489 Eliminated extra register and fixed ports to icache. Still need to support physical tag check and write in icache memory. Still need to reduce to 1 port SRAM in icache. I would like to refactor the icache code. Ross Thompson 2021-05-03 12:03:17 -0500
  • c643372e1d merge conflict resolved -- Ross and I made the same fix bbracker 2021-05-03 10:10:42 -0400
  • 9ab714e636 small rv64 plic test bugfix bbracker 2021-05-03 10:06:44 -0400
  • c7b97d0339 Added back in function name to wave.do Ross Thompson 2021-05-03 09:04:48 -0500
  • c0a4b7cb17 Fixed typo in ifu for bypassing branch predictor. Fixed missing signal name in local history predictor. Ross Thompson 2021-05-03 08:56:45 -0500
  • a37d9b5e8e Fixed lint error in div David Harris 2021-05-03 09:26:12 -0400
  • 9bde239143 ifu lint fixes bbracker 2021-05-03 09:25:22 -0400
  • 2368b58cc9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-05-03 09:23:52 -0400
  • b98bc89f76 ok should be the final parsing script change from me Noah Boorstin 2021-05-03 01:37:24 -0400
  • f6acec191a buildroot: add one final utility script Noah Boorstin 2021-05-03 01:28:09 -0400
  • b32128465c busybear: remove now unneeded hack for fixed CSR issue Noah Boorstin 2021-05-01 15:16:54 -0400
  • db95151d8d fpu imperas tests run Katherine Parry 2021-05-01 02:18:01 +0000
  • 1fcd43e844 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-04-30 06:26:35 -0400
  • 182bfdbb0e rv32 plic test and lint fixes bbracker 2021-04-30 06:26:31 -0400
  • 48d32c1daf rollback regression to 400k instrs for busybear Noah Boorstin 2021-04-29 20:59:30 -0400
  • d03ca20dc9 Make vectored interrupt trap handling work, and add tests for mtvec with vectored interrupts Domenico Ottolia 2021-04-29 20:42:14 -0400
  • 818c0abc89 Fixed memory size in configs for rv32ic and rv64ic. Removed warning on call to $fscanf. Ross Thompson 2021-04-29 17:36:46 -0500
  • 61beedf275 Add .S files for new mcause and scause tests Domenico Ottolia 2021-04-29 16:48:56 -0400
  • c60c4f4adc Minor improvements to scause test Domenico Ottolia 2021-04-29 16:48:07 -0400
  • 4c938a6846 Add .S and .reference_output files for mie tests Domenico Ottolia 2021-04-29 16:40:48 -0400
  • c8a81779ca Add machine-mode timer interrupts to mcause tests Domenico Ottolia 2021-04-29 16:39:18 -0400
  • 6e5fc107d9 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Thomas Fleming 2021-04-29 16:30:00 -0400
  • 6fc04768f5 Same but don't break sim-wally this time Domenico Ottolia 2021-04-29 15:33:27 -0400
  • 7ae5d4d11e Add more exceptions to medeleg tests Domenico Ottolia 2021-04-29 15:32:13 -0400
  • 9dfbfd5772 fix to pcm bug ushakya22 2021-04-29 15:21:08 -0400
  • 77210527c1 Working MIE timer tests ushakya22 2021-04-29 15:19:43 -0400
  • 4fae8088e3 Add medeleg tests Domenico Ottolia 2021-04-29 15:02:36 -0400
  • bf54c9b0b2 Enhance lint-wally functionality Jarred Allen 2021-04-29 14:48:41 -0400
  • ebd9c0ee29 Remove signal which no longer exists from default waves, so sim-wally works Jarred Allen 2021-04-29 14:41:10 -0400
  • 8fd9cc679b Fix compile error in branch predictor Jarred Allen 2021-04-29 14:36:56 -0400
  • 1e57c6bb92 fixed bug in gshare, global and local history BP Shreya Sanghai 2021-04-29 06:14:32 -0400
  • 5f2bccd88f Clean up PMA checker and begin PMP checker Thomas Fleming 2021-04-29 02:20:39 -0400
  • c62fdfb7b3 Remove unused waves from .do files Thomas Fleming 2021-04-29 02:19:46 -0400
  • 1e9dec537a Supply reference output for mmu64 test Thomas Fleming 2021-04-29 02:19:12 -0400
  • 111ad35fe3 Copy mmu reference output files to work dir Thomas Fleming 2021-04-28 20:01:34 -0400
  • 18e0b353a9 Add mmu waves (commented) to busybear Thomas Fleming 2021-04-28 20:01:05 -0400
  • a4dad3403e same but do that right this time Noah Boorstin 2021-04-28 14:27:12 -0400
  • 18ecea4506 Make privileged makefiles actually execute tests when you say they should (compile-only is still default) Domenico Ottolia 2021-04-27 23:09:01 -0400
  • 60dc6aaf48 Modify make file to make privileged tests always pass Imperas (for testing interrupts) & Add mtvec/stvec tests Domenico Ottolia 2021-04-27 21:47:38 -0400
  • 44606b6c19 busybear: respect branch predictor disable config Noah Boorstin 2021-04-27 15:40:31 -0400
  • 8ae28e7887 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Ross Thompson 2021-04-26 14:28:09 -0500
  • 72363f5c66 Added the ability to exclude branch predictor. Ross Thompson 2021-04-26 14:27:42 -0500
  • ff1a6b63ed ok but do that better Noah Boorstin 2021-04-26 14:38:05 -0400
  • 0324329ed9 linux: start using internal branch predictor signal Noah Boorstin 2021-04-26 14:34:38 -0400
  • afbb100860 Fixed issue with not saving the first cache block read on a miss spill. Ross Thompson 2021-04-26 12:57:34 -0500
  • ee628e388a minor busybear fixes Noah Boorstin 2021-04-26 13:24:39 -0400
  • 0850c18cb7 minor parsing updates Noah Boorstin 2021-04-26 13:11:01 -0400
  • 8e5409af66 Icache integrated! Merge branch 'icache-almost-working' into main Ross Thompson 2021-04-26 11:48:58 -0500
  • 467a463c13 Reverted back the exe2memfile.pl script changes. Something I changed broke the load tests. Ross Thompson 2021-04-26 10:44:27 -0500
  • 31a0387136 merge cleanup; mem init is broken bbracker 2021-04-26 08:00:17 -0400
  • ba94fa3436 it says I need to merge in order to pull bbracker 2021-04-26 07:46:24 -0400
  • 1cc0dcc83f progress on bus and lrsc bbracker 2021-04-26 07:43:16 -0400
  • 6e803b724e Merge branch 'tests' into icache-almost-working Ross Thompson 2021-04-25 21:25:36 -0500
  • 4f8ec22d7f buildroot: change to new image Noah Boorstin 2021-04-25 15:15:14 -0400
  • 42fea2322e busybear: hopefully last parser changes of the semester Noah Boorstin 2021-04-25 14:08:18 -0400
  • a6f81f5dc0 parsing scripts update Noah Boorstin 2021-04-24 21:56:16 -0400
  • 86946266cf thomas fixed it before I did bbracker 2021-04-24 09:38:52 -0400
  • a3487a9e47 do script refactor bbracker 2021-04-24 09:32:09 -0400