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  • a3823ce3a9 commented out old hack that used hardcoded addresses bbracker 2021-07-20 15:03:55 -0400
  • e5e3f5abe6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-07-20 14:46:58 -0400
  • 1f3dfa20f6 flag for optional boottim David Harris 2021-07-20 14:46:37 -0400
  • 4c785845f3 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-07-20 13:27:58 -0500
  • 00081ebc68 Replaced FinalReadDataM with ReadDataM in dcache. Ross Thompson 2021-07-20 13:27:29 -0500
  • 89dc9ba6e4 Updated riscv64-unknown-elf-gcc location so that it can be easily accessed Abe 2021-07-20 14:18:13 -0400
  • 6b72b1f859 ignore mhpmcounters because QEMU doesn't implement them bbracker 2021-07-20 13:37:52 -0400
  • 93ea2000dc Updated MMU tests to use shared library in assembly Kip Macsai-Goren 2021-07-20 12:35:30 -0400
  • a1ea654b11 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-07-20 12:08:46 -0400
  • e1a1a8395e Parameterized I$/D$ configurations and added sanity check assertions in testbench David Harris 2021-07-20 08:57:13 -0400
  • 077662bfa1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-07-20 05:40:49 -0400
  • 9e658466e6 testbench hack to ignore MTVAL for illegal instr faults; testbench upgrade to not check PCW for illegal instr faults; testbench hack to not check speculative instrs following an MRET (it seems MRET has 1 stage more latency than a branch instr) bbracker 2021-07-20 05:40:39 -0400
  • 12e09a7ace slight mod to fpdiv - still bug in batch vs. non-batch James E. Stine 2021-07-20 01:47:46 -0400
  • 3b10ea9785 major fixes to CSR checking bbracker 2021-07-20 00:22:07 -0400
  • 365485bd8b Added performance counters for dcache access and dcache miss. Ross Thompson 2021-07-19 22:12:20 -0500
  • 508c3e35af Restored TIM range. Ross Thompson 2021-07-19 21:17:31 -0500
  • 99fa2bbbc3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-07-19 19:30:40 -0400
  • cb15d7e4c7 change debugBuildroot because GDB formatted list is now 50 lines long per instruction (we lost 6 CSRs on the whole) bbracker 2021-07-19 19:30:29 -0400
  • 23b76a724d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-07-19 18:19:59 -0400
  • 4d40b5faef Added cache configuration to config files David Harris 2021-07-19 18:19:46 -0400
  • c1d63fe77c MemRWM shouldn't factor into PCD checking bbracker 2021-07-19 18:03:30 -0400
  • 4d10cfc98b create qemu_output.txt bbracker 2021-07-19 18:02:41 -0400
  • c8203c171e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-07-19 17:11:49 -0400
  • f7d040af1e make testbench ignore MIP because of timing imprecision and because QEMU maybe isn't getting MTIP right anyways bbracker 2021-07-19 17:11:42 -0400
  • 5880cbafe4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2021-07-19 16:46:46 -0400
  • 1aeef4e7d1 remove busybear from regression because it is not keeping up with buildroot's changes to testbench-linux bbracker 2021-07-19 16:22:05 -0400
  • bc5222e721 put MTIMECMP's reset value back to 0 because the reset value of -1 broke the MCAUSE tests bbracker 2021-07-19 16:19:24 -0400
  • f17f6cea56 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-07-19 15:42:26 -0400
  • 65df5c087b adapt testbench to removal of ReadDataWEn signal bbracker 2021-07-19 15:42:14 -0400
  • ae5663a244 adapt testbench to removal of signal bbracker 2021-07-19 15:41:50 -0400
  • 64e0fe4c5a whoops MTIMECMP is always 64 bits bbracker 2021-07-19 15:40:53 -0400
  • 69c6a7d2cc Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Abe 2021-07-19 15:20:38 -0400
  • 5990ed23a4 removed Wally test framwork include statement kipmacsaigoren 2021-07-19 19:15:11 +0000
  • bdb1ece183 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-07-19 15:13:14 -0400
  • cd469035be make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset bbracker 2021-07-19 15:13:03 -0400
  • 2614df627e added changes to priority encoders from synthesis branch (correctly this time I hope) Kip Macsai-Goren 2021-07-19 15:06:14 -0400
  • bf3ca50a9a Furture simplification of the dcache ReadDataW update. Ross Thompson 2021-07-19 12:46:31 -0500
  • 9f76e1d64d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-07-19 12:32:35 -0500
  • b61dad4b83 Fixed a complex bug in the dcache, where back to back loads would lose data on the load before a stall occurred. The solution was to modify the logic for SelAdrM in the dcache so that a stall would cause the SRAM to reread the address in the Memory stage rather than Execution stage. This also required updating the ReadDataWEn control so it is always enabled on ~StallW. Ross Thompson 2021-07-19 12:32:16 -0500
  • 1b0b9d0f79 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-07-19 13:21:04 -0400
  • f31a0ded75 change buildroot expectations to match reality bbracker 2021-07-19 13:20:53 -0400
  • 93820169f1 rename page table levels Kip Macsai-Goren 2021-07-19 13:00:59 -0400
  • 3d878ff4c0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2021-07-19 13:00:25 -0400
  • 4d53b9002f Broken. Possible change to walker, dcache, tlb addressing. Improves the naming of address signals. But has a problem when the walker finishes the dcache does not get the correct address on the cycle the DTLB is updated. This leads to incorrect index selection in the dcache. Ross Thompson 2021-07-19 10:33:27 -0500
  • 67eb1f5c6b change sram1rw to have a small delay so that we don't have signals changing on clock edges bbracker 2021-07-19 11:30:07 -0400
  • 55fc939ac6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2021-07-19 10:56:48 -0400
  • ab142300ef Revert "added priority circuit to attempt to remove delay due to rippling in pmpadrdec" Kip Macsai-Goren 2021-07-19 10:46:17 -0400
  • 2ed6285a3d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-07-19 10:34:18 -0400
  • e4a9abc16c added priority circuit to attempt to remove delay due to rippling in pmpadrdec Kip Macsai-Goren 2021-07-13 19:11:50 -0400
  • 7d571f27a6 delete sbtm_a4 and sbtm_a5 as they are not needed James Stine 2021-07-19 08:06:00 -0500
  • 186b5dee69 remove sbtm3.sv - not needed James Stine 2021-07-19 08:00:53 -0500
  • 5b1f9797f5 update part I on sbtm change James Stine 2021-07-19 07:59:27 -0500
  • 8e01007d1c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-07-19 00:25:06 -0400
  • 60769388a0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Abe 2021-07-18 23:09:57 -0400
  • c9180f4ebd FDIV and FSQRT passes when simulating in modelsim Katherine Parry 2021-07-18 23:00:04 -0400
  • 2a33526f8e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-07-18 21:50:05 -0400
  • e4a50a5bb8 change memread testvectors to not left-shift bytes and half-words bbracker 2021-07-18 21:49:53 -0400
  • 46ab609498 Updated FMA1 with parameterized size David Harris 2021-07-18 20:40:49 -0400
  • dcc690a938 temp fpdivsqrt James E. Stine 2021-07-18 20:04:18 -0400
  • 5e9dcb3f1c linux testbench progress bbracker 2021-07-18 18:47:40 -0400
  • ed64d37e65 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-07-18 17:36:29 -0400
  • 4f8f52f283 Added FLEN, NE, NF to config and started using these in FMA1 David Harris 2021-07-18 17:28:25 -0400
  • 60dabb9094 fdivsqrt inegrated, but not completley working Katherine Parry 2021-07-18 14:03:37 -0400
  • 8317be5aed Renamed pagetablewalker to hptw David Harris 2021-07-18 04:11:33 -0400
  • c75d70126f LSUArb: Removed Demuxes on ReadDataW, DataMiisalignedM, HPTWStall David Harris 2021-07-18 03:51:30 -0400
  • 3f7a3b280e HPTW: Simpliifieid PRegEn David Harris 2021-07-18 03:35:38 -0400
  • 60bd27a40e Removed EndWalk signal and simplified TLBMissReg David Harris 2021-07-18 03:26:43 -0400
  • 14220684b6 Fixed bug with rv32a/WALLY-LRSC test in imperas. Minor issue. Ross Thompson 2021-07-17 21:02:24 -0500
  • 009c5314b4 Fixed LRSC in 64bit version. 32bit version is broken. Ross Thompson 2021-07-17 20:58:49 -0500
  • 8bdf1eaf0f added lrsc.sv David Harris 2021-07-17 21:15:08 -0400
  • 8d348dacce Started atomics David Harris 2021-07-17 21:11:41 -0400
  • 574f7d9c32 moved subwordread to lsu David Harris 2021-07-17 20:37:20 -0400
  • e82374d19f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-07-17 20:01:23 -0400
  • 9a86fc899b LSU cleanup David Harris 2021-07-17 20:01:03 -0400
  • d9750c16a5 Pushing HPTWPAdrM flop into LSUArb David Harris 2021-07-17 19:39:18 -0400
  • 586341a41a Simplified VPN case statement David Harris 2021-07-17 19:34:01 -0400
  • 9cfbc4aec0 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-07-17 18:27:44 -0500
  • 35b7577be2 Finished HPTW TranslationPAdr simlification David Harris 2021-07-17 19:27:24 -0400
  • 1aac97030a Before returning to the ready state the dcache must set SelAdr = 0 on the cycle before. Ross Thompson 2021-07-17 17:56:40 -0500
  • 2b1fdfbae2 Further TranslationVAdr simplification David Harris 2021-07-17 19:24:37 -0400
  • b785a20f90 Continued Translation Address Cleanup of TranslationPAdrMux David Harris 2021-07-17 19:16:56 -0400
  • fc88b3a693 Continued Translation Address Cleanup David Harris 2021-07-17 19:09:13 -0400
  • 6536ef8dce Refining address interface between HPTW and LSU David Harris 2021-07-17 19:02:18 -0400
  • 7b92e7e590 Fixed bad register in I-FSD-01 Imperas test. David Harris 2021-07-17 17:08:07 -0400
  • a67292b5f3 trap.sv comment cleanup David Harris 2021-07-17 16:01:07 -0400
  • c1c3249709 trap.sv cleanup David Harris 2021-07-17 15:57:10 -0400
  • af5e1f7f39 Finished removing PageTableEntry redundant signals from hptw David Harris 2021-07-17 15:50:52 -0400
  • e182cac9bc hptw: Removed NonBusTrapM from LSU David Harris 2021-07-17 15:24:26 -0400
  • 2f81e4c70d hptw: Removed NonBusTrapM from LSU David Harris 2021-07-17 15:22:24 -0400
  • 428a9c1ca3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-07-17 15:11:43 -0400
  • 863e6e72d6 hptw: Propagating PageTableEntryF removal through IFU David Harris 2021-07-17 15:04:39 -0400
  • a855e0170e hptw: Propagating PageTableEntryF removal through LSU David Harris 2021-07-17 15:01:01 -0400
  • 8d65d50085 separated buildroot debugging from buildroot logging bbracker 2021-07-17 14:52:34 -0400
  • d4eeabe355 hptw: Unified PageTableEntryM and PageTableEntryF outputs of pagetablewalker into PTE David Harris 2021-07-17 14:48:44 -0400
  • 82fc766819 swapped out linux testbench signal names bbracker 2021-07-17 14:48:12 -0400
  • 18fb282a37 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-07-17 14:46:38 -0400
  • 4a3503281f swapped out linux testbench signal names bbracker 2021-07-17 14:46:18 -0400
  • 86e04c080d hptw: Added ValidLeaf and ValidNonLeaf for readability, renamed _WDV to _READ states David Harris 2021-07-17 14:36:27 -0400
  • 714eef4a1a hptw: Eliminated A and D bit faults while walking page table, per spec David Harris 2021-07-17 14:29:20 -0400
  • 90c5312f85 hptw: Simplified TranslationVAdr calculation based just on DTLBWalk David Harris 2021-07-17 14:16:33 -0400