Ross Thompson
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fc7016eea6
|
Fixed the AMO dcache bug. The subword write needs to occur before the AMO logic.
Fixed logic for trace update in the M and W stages. The M stage should not update if there
is an instruction fault.
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2021-08-08 00:28:18 -05:00 |
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Ross Thompson
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aa9a5d879b
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Finally past the CLINT issues.
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2021-08-06 16:41:34 -05:00 |
|
Ross Thompson
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0bfbcef8ab
|
Now past the CLINT issues.
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2021-08-06 16:16:39 -05:00 |
|
Ross Thompson
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9be10cdc8b
|
Partial conversion of the linux trace checking to read in the file in the Memory Stage so it is possible to overwrite registers, memory, and interrupts.
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2021-08-06 16:06:50 -05:00 |
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Ross Thompson
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c749d08542
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fixed the read timer issue but we still have problems with interrupts and i/o devices.
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2021-08-06 10:16:06 -05:00 |
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Ross Thompson
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3582be4dbb
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Fixed issue with desync of PCW and ExpectedPCW in linux test bench. The ERROR macro had a 10 ns delay which caused the trace to skip 1 instruction.
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2021-08-05 16:49:03 -05:00 |
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Ross Thompson
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f808b29065
|
Added some comments to linux testbench.
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2021-07-30 17:57:03 -05:00 |
|
Ross Thompson
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e166cc84ee
|
Patched up changes for wally-pipelined.do and wally-buildroot.do to support moved common testbench files.
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2021-07-30 14:24:50 -05:00 |
|
Ross Thompson
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74fba4bb06
|
Moved the test bench modules to a common directory.
|
2021-07-30 14:16:14 -05:00 |
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Ross Thompson
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d8878581f4
|
Created new linux test bench and parsing scripts.
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2021-07-29 20:26:50 -05:00 |
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Kip Macsai-Goren
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3008111bcd
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added tests for 64/32 bit pma/pmp checker. They compile, but skip OVPsim simulation. They DO NOT pass regression yet
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2021-07-23 16:02:42 -04:00 |
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Kip Macsai-Goren
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381a93b45b
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added sfence to legal instructions, zeroed out rom file to populate for tests
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2021-07-23 15:55:08 -04:00 |
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Kip Macsai-Goren
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da9ead2d95
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-23 15:16:01 -04:00 |
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bbracker
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0e64b99dc0
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testbench workaround for QEMU's SSTATUS XLEN bits
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2021-07-23 14:00:44 -04:00 |
|
Kip Macsai-Goren
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52faa22774
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include SFENCE.VMA in legal instructions
|
2021-07-22 20:24:24 -04:00 |
|
David Harris
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21a65f45cd
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Partial work on Unpacking exponents to larger word size. FCVT and FMA are presently broken.
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2021-07-22 14:18:27 -04:00 |
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bbracker
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cca16cc5b4
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-21 20:07:03 -04:00 |
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bbracker
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6e460c5032
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replace physical address checking with virtual address checking because address translator is broken
|
2021-07-21 19:47:13 -04:00 |
|
Katherine Parry
|
01f0b4e5df
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FDIV and FSQRT work
|
2021-07-21 14:08:14 -04:00 |
|
Katherine Parry
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b9081e514c
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FMA parameterized
|
2021-07-20 22:04:21 -04:00 |
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bbracker
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f9b6bd91f5
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fix PC checking during InstrPageFault; fix order of S-mode CSR checking; rename peripheral scopes to not be genblk
|
2021-07-20 17:55:44 -04:00 |
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bbracker
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a02694a529
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-07-20 15:04:13 -04:00 |
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bbracker
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a3823ce3a9
|
commented out old hack that used hardcoded addresses
|
2021-07-20 15:03:55 -04:00 |
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David Harris
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e5e3f5abe6
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-07-20 14:46:58 -04:00 |
|
David Harris
|
1f3dfa20f6
|
flag for optional boottim
|
2021-07-20 14:46:37 -04:00 |
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bbracker
|
6b72b1f859
|
ignore mhpmcounters because QEMU doesn't implement them
|
2021-07-20 13:37:52 -04:00 |
|
bbracker
|
a1ea654b11
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-07-20 12:08:46 -04:00 |
|
David Harris
|
e1a1a8395e
|
Parameterized I$/D$ configurations and added sanity check assertions in testbench
|
2021-07-20 08:57:13 -04:00 |
|
bbracker
|
9e658466e6
|
testbench hack to ignore MTVAL for illegal instr faults; testbench upgrade to not check PCW for illegal instr faults; testbench hack to not check speculative instrs following an MRET (it seems MRET has 1 stage more latency than a branch instr)
|
2021-07-20 05:40:39 -04:00 |
|
bbracker
|
3b10ea9785
|
major fixes to CSR checking
|
2021-07-20 00:22:07 -04:00 |
|
bbracker
|
c1d63fe77c
|
MemRWM shouldn't factor into PCD checking
|
2021-07-19 18:03:30 -04:00 |
|
bbracker
|
f7d040af1e
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make testbench ignore MIP because of timing imprecision and because QEMU maybe isn't getting MTIP right anyways
|
2021-07-19 17:11:42 -04:00 |
|
bbracker
|
65df5c087b
|
adapt testbench to removal of ReadDataWEn signal
|
2021-07-19 15:42:14 -04:00 |
|
bbracker
|
ae5663a244
|
adapt testbench to removal of signal
|
2021-07-19 15:41:50 -04:00 |
|
bbracker
|
cd469035be
|
make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset
|
2021-07-19 15:13:03 -04:00 |
|
Katherine Parry
|
c9180f4ebd
|
FDIV and FSQRT passes when simulating in modelsim
|
2021-07-18 23:00:04 -04:00 |
|
bbracker
|
5e9dcb3f1c
|
linux testbench progress
|
2021-07-18 18:47:40 -04:00 |
|
Katherine Parry
|
60dabb9094
|
fdivsqrt inegrated, but not completley working
|
2021-07-18 14:03:37 -04:00 |
|
Ross Thompson
|
14220684b6
|
Fixed bug with rv32a/WALLY-LRSC test in imperas. Minor issue.
|
2021-07-17 21:02:24 -05:00 |
|
David Harris
|
8d348dacce
|
Started atomics
|
2021-07-17 21:11:41 -04:00 |
|
bbracker
|
82fc766819
|
swapped out linux testbench signal names
|
2021-07-17 14:48:12 -04:00 |
|
David Harris
|
87aa527de7
|
hptw: minor cleanup
|
2021-07-17 13:40:12 -04:00 |
|
David Harris
|
ef63e1ab52
|
hptw: factored pregen
|
2021-07-17 11:11:10 -04:00 |
|
David Harris
|
dac22d5016
|
Removed more unused signals from ahblite
|
2021-07-17 02:21:54 -04:00 |
|
Kip Macsai-Goren
|
d10fd25c33
|
included virtual memory tests in testbench
|
2021-07-16 17:57:24 -04:00 |
|
Ross Thompson
|
5e18a15a4c
|
Added guide for Ben to do linux conversion.
|
2021-07-16 15:04:30 -05:00 |
|
Ross Thompson
|
6521d2b468
|
Also changed the shadow ram's dcache copy widths.
Merge branch 'dcache' into main
|
2021-07-16 14:21:09 -05:00 |
|
Ross Thompson
|
e5d624c1fa
|
Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault.
|
2021-07-15 11:56:35 -05:00 |
|
Ross Thompson
|
fa26aec588
|
Merge branch 'main' into dcache
|
2021-07-15 11:55:20 -05:00 |
|
Ross Thompson
|
b9902b0560
|
Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits.
|
2021-07-15 11:00:42 -05:00 |
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