David Harris
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f483e8002a
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Lint cleanup
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2021-10-23 08:39:21 -07:00 |
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David Harris
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e2e950ac0f
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Cleaned up LINT erors
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2021-10-23 06:28:49 -07:00 |
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David Harris
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4c480a40f6
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-10-23 06:15:49 -07:00 |
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David Harris
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3249d65209
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Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience.
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2021-10-23 06:15:26 -07:00 |
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kipmacsaigoren
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ef297067e9
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removed reduntant definitions for FPU in MISA.
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2021-10-22 15:18:25 -05:00 |
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James E. Stine
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f6e8e45901
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Modify register before fpdivsqrt to be synthesizable for FPGAs and better in tune for ASIC clocking
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2021-10-22 13:41:50 -05:00 |
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Katherine Parry
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7c7c0f538a
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put the FMA priority encoders into their own module
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2021-10-22 10:03:12 -07:00 |
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James E. Stine
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0dcca43f48
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Get rid of lint warning - still need more testing though
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2021-10-21 15:19:22 -05:00 |
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James E. Stine
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dd7dbaa382
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Clean up some FPU and add pipelined fpdivsqrt to fpu.sv
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2021-10-21 13:52:12 -05:00 |
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James E. Stine
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bafb3a983d
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Fix fpdivsqrt lint error on CPA for convergence
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2021-10-20 17:46:13 -05:00 |
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David Harris
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ceaf84a3ce
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removed .* from wallypipeliendsoc
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2021-10-20 13:49:18 -07:00 |
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James E. Stine
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71b48048da
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Added pipelined version of fpdivsqrt as well as analysis of fpdivsqrt to cut multiplier down to 60bits.
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2021-10-20 12:00:41 -05:00 |
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David Harris
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47e19d4caa
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moved coemark and testsBP to tests
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2021-10-20 09:10:06 -07:00 |
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David Harris
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23b3d7dbc1
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Move tests into subdirectory and moved wavedrom out of project
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2021-10-20 09:03:21 -07:00 |
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David Harris
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a88af1841f
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radix 2 SRT checkin
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2021-10-19 14:08:16 -07:00 |
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James E. Stine
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41010aa418
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Some more sanitization but will pass to legal to determine if okay on version - it is substantially different in some ways but not a legal expert on this
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2021-10-19 12:09:43 -05:00 |
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James E. Stine
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a75abb04bd
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Modify DW02_multp to properly list the correct number of bits at the output (i.e., 2*WIDTH + 2).
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2021-10-19 11:58:06 -05:00 |
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David Harris
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3bc985d230
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Changed some flops to settable
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2021-10-18 17:05:29 -07:00 |
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David Harris
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0516ee768b
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replaced flopenl with flopenr when clearing to 0
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2021-10-18 16:53:18 -07:00 |
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David Harris
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398337951d
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-10-18 15:44:31 -07:00 |
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David Harris
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00d8035836
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Fixed multiplier and pointed arch tests to new path in addins
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2021-10-18 15:43:59 -07:00 |
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Ross Thompson
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cd58a388e4
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fixed issues with dc shell not liking modules with parameters without default values.
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2021-10-18 17:24:15 -05:00 |
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James E. Stine
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37fe5e56a8
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Sanitization some more on mult_cs.sv
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2021-10-18 05:24:16 -05:00 |
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James E. Stine
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d0ab43e4e8
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Update some on mult_cs and delete DW02_mult.v
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2021-10-18 05:06:49 -05:00 |
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James E. Stine
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de7b673e34
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Add hacky hand-made carry/save multiplier - will improve
|
2021-10-16 10:37:29 -05:00 |
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Katherine Parry
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c34633804a
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cvtfp module documented
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2021-10-14 15:25:31 -07:00 |
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James E. Stine
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c5b99300e7
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Clean up some signals - beautification onging
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2021-10-14 17:12:00 -05:00 |
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Kip Macsai-Goren
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869c35ba1c
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Fixed typo in imperas64mmu tests causing PMP tests not to run.
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2021-10-14 13:42:24 -07:00 |
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Skylar Litz
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71397d5db9
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-10-13 15:38:32 -07:00 |
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Skylar Litz
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4ca4e13ba2
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add StallM signal back to DivStartE control
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2021-10-13 15:34:40 -07:00 |
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James E. Stine
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1dba57dce7
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Update to fpdivsqrt to go on posedge as it should. Also an update to
individual regression test for TestFloat (still needs some tweaking)
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2021-10-13 17:14:42 -05:00 |
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bbracker
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4abc6fc915
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change infrastructure to expect only 6.3 million from buildroot
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2021-10-12 10:41:15 -07:00 |
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Shreya Sanghai
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4424006624
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added DESIGN_COMPLIER to forgotten config files
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2021-10-12 10:14:04 -07:00 |
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Katherine Parry
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b79021a73e
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lint warnings fixed
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2021-10-12 09:45:02 -07:00 |
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Katherine Parry
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539d21645f
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some fpu lint warnings fixed - still working on it
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2021-10-11 18:32:03 -07:00 |
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Shreya Sanghai
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0acf9fd746
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made redunantmul generate DW02_multp for synopsys sythnesis
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2021-10-11 11:54:39 -07:00 |
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Shreya Sanghai
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84ff2b49c7
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actually added redundant mul
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2021-10-11 11:29:13 -07:00 |
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David Harris
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af7903e1b2
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-10-11 11:21:39 -07:00 |
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David Harris
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1cdc5db75d
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Extended lint to check rv32/64g (including fpu. Not clean yet.
|
2021-10-11 11:20:42 -07:00 |
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Shreya Sanghai
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a1c9ffdf2b
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added redundant multiplier
|
2021-10-11 11:20:12 -07:00 |
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David Harris
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ab6a796690
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Starting to optimize multiplier
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2021-10-11 11:06:07 -07:00 |
|
David Harris
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f1190b6ceb
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intdiv cleanup
|
2021-10-11 08:14:21 -07:00 |
|
David Harris
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4139f27d10
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Divider FSM simplification
|
2021-10-10 22:24:14 -07:00 |
|
David Harris
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75c17dc372
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Major reorganization of regression and simulation and testbenches
|
2021-10-10 15:07:51 -07:00 |
|
James E. Stine
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2b66615812
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Update to missing vectors :P and also run_all script. Also made all scripts .sh as technically run using SH
|
2021-10-10 15:44:01 -05:00 |
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bbracker
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13352eccda
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-10-10 13:12:44 -07:00 |
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bbracker
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161767cddd
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make regression expect what buildroot is actually able to reach
|
2021-10-10 13:12:36 -07:00 |
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David Harris
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a6c6b2b974
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-10-10 12:26:15 -07:00 |
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David Harris
|
caf3c2de9b
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-10-10 12:25:11 -07:00 |
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bbracker
|
90ccd60790
|
simplify flopenrc's that didn't actually need to be flopenrc's
|
2021-10-10 12:25:05 -07:00 |
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