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Author SHA1 Message Date
Ross Thompson
fdd7b68501 Signal renames for PC*NextF and SelSpillNextF. 2022-12-30 14:21:20 -06:00
Cedar Turek
158e23b5a5 commented complicated step/right shift calc 2022-12-30 12:03:10 -08:00
Cedar Turek
eef1d4dd66 comment cleaning 2022-12-30 11:11:34 -08:00
Cedar Turek
7e5cafeda3 Described internal signals of fdivsqrt top 2022-12-30 11:01:02 -08:00
Cedar Turek
8cb4a7a69a Commented fdivsqrt module 2022-12-30 10:52:25 -08:00
Ross Thompson
ed536dd142 Removed da page fault from spill logic. 2022-12-30 12:51:56 -06:00
Cedar Turek
3115df9380 Begin commenting divsqrt 2022-12-30 10:43:02 -08:00
Ross Thompson
80a135f101 Spill only occurs on 32-bit instructions. 2022-12-30 12:41:25 -06:00
Katherine Parry
aca6f0d4e6 removed ethe second bit from fma alignment shift 2022-12-30 12:07:44 -06:00
Ross Thompson
b1f68a1d85 Modified IROM to return the correct offset when unaligned. 2022-12-30 11:48:40 -06:00
Katherine Parry
3adb8efb2b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-30 11:02:04 -06:00
Ross Thompson
6cf5a99b5d Updated constraints to remove DivBusyE. 2022-12-30 10:51:35 -06:00
Katherine Parry
5844a596a3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-30 09:56:35 -06:00
David Harris
58218dbdd1 continued simplifying integer division special cases 2022-12-30 07:40:28 -08:00
David Harris
bd16fd79d4 started simplifying integer division special cases 2022-12-30 07:34:26 -08:00
David Harris
30dc45c764 removed duplicate quotient mux 2022-12-30 07:17:38 -08:00
David Harris
61230c967c simplified sign handling mux 2022-12-30 07:10:47 -08:00
David Harris
ba976d66e4 Radix 4 divsqrt 2022-12-30 07:01:44 -08:00
David Harris
3c475455d9 Clean up sqrt preproc 2022-12-30 07:00:48 -08:00
David Harris
4fb8396867 Clean up sqrt initialization mux 2022-12-30 06:55:20 -08:00
David Harris
dba3ffe767 Reduced size of preproc right shift 2022-12-30 06:47:40 -08:00
David Harris
0e9bd5dab5 fdivsqrtpreproc shift simplification 2022-12-30 06:45:51 -08:00
David Harris
e9b314f902 fdiv cleanup, reduce number of rv32f fma_b15 tests being run to speed up regression 2022-12-30 06:40:25 -08:00
David Harris
ef37070eee Fixed register timing failure on SpecialCaseM in fdivsqrt 2022-12-29 21:09:23 -08:00
Ross Thompson
872ff619e3 Fixed problems with changes to ram2p. 2022-12-29 17:13:48 -06:00
Ross Thompson
c725b5534a Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-29 17:07:53 -06:00
Ross Thompson
654b10894c Re-enabled the branch predictor in rv64gc. 2022-12-29 17:07:50 -06:00
Katherine Parry
90eb4fc1f1 minor optimizations and renaming 2022-12-29 15:54:17 -06:00
Katherine Parry
89e8df084a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-29 12:37:51 -06:00
David Harris
776f4714af Clean up names and comments in divsqrt 2022-12-29 08:02:44 -08:00
David Harris
6664cb9db4 Factored out hardware unique to RV64 and to IDIV 2022-12-29 07:36:26 -08:00
Katherine Parry
1b4fa38510 one bitt removed from inital lignment shift 2022-12-28 17:46:53 -06:00
Alessandro Maiuolo
7c19665dea added script in pipelined folder to run regressions with all radix/copies configurations 2022-12-28 07:32:35 -08:00
David Harris
7780b44973 fdivsqrtfsm conditional on IDIV (fixed typo) 2022-12-27 22:16:48 -08:00
David Harris
5ee44b7405 fdivsqrtfsm conditional on IDIV 2022-12-27 22:15:45 -08:00
David Harris
db933aa7e2 fdivsqrtfsm conditional on IDIV 2022-12-27 22:14:09 -08:00
Cedar Turek
ef360f0539 idiv passing radix 2, four copies 2022-12-27 22:11:18 -08:00
Cedar Turek
4ed2c6255c idiv passing radix 2, four copies 2022-12-27 22:10:48 -08:00
David Harris
9964fc9ebe Moved IDIV in fdivsqrtfms into generate block 2022-12-27 22:04:50 -08:00
David Harris
a832605658 Moved IDIV for postproc into generate block 2022-12-27 22:02:14 -08:00
David Harris
d59878a886 Moved IDIV_ON_FP into conditional block in fdivsqrtpreproc 2022-12-27 21:53:00 -08:00
Cedar Turek
a559abe554 Fixed cycles for multiple iterations. 2-copies radix 2 passing regression. 2022-12-27 21:34:27 -08:00
David Harris
665b545fd0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-27 21:30:13 -08:00
David Harris
87abed6722 cleanup 2022-12-27 21:29:36 -08:00
David Harris
6cf73cdaee Fixed floating Sqrt signal when floating point is disabled, causing REMU tohang during buildroot around 3.2M 2022-12-27 21:24:38 -08:00
David Harris
c08811357c Renamed muldiv to mdu 2022-12-27 19:57:10 -08:00
Ross Thompson
a129e27502 signal name changes in ram2p. 2022-12-27 15:07:01 -06:00
Ross Thompson
66b2fbd836 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-27 15:06:25 -06:00
Ross Thompson
3f4b3a4159 Added about moving decompressed config generate. 2022-12-27 15:04:55 -06:00
David Harris
dfc0b5d1ad Removed MDUE from unnecessary places in fdivsqrt 2022-12-27 10:42:40 -08:00