Ross Thompson
50b307bc0e
Looks like rdtime was accidentally replaced with rrame from a find and replace.
2021-12-20 21:26:38 -06:00
David Harris
a25d541dcf
Moved generate of conditional units to hart
2021-12-19 17:03:57 -08:00
David Harris
3c3bfd055e
Moved generate statements for optional units into wallypipelinedhart
2021-12-19 16:53:41 -08:00
Ross Thompson
d9cc9afd49
Changes to buildroot to support MemAdrM to IEUAdrM name changes.
2021-12-19 18:24:40 -06:00
David Harris
aebd746e71
Renamed MemAdrE to IEUAdrE and moved the MemAdrM flop from IEU to LSU to reduce wires crossing hierarchies
2021-12-15 12:10:45 -08:00
David Harris
865d5ce0b1
Renamed dtim->ram and boottim ->bootrom
2021-12-14 13:43:06 -08:00
bbracker
5feccaec68
fix release of ReadDataM
2021-12-08 14:11:43 -08:00
bbracker
979580b1e7
fix checkpointing so that it can find the synchronized reset signal
2021-12-07 13:12:06 -08:00
Skylar Litz
546f7fb4c2
fix some interrupt timing bugs
2021-12-03 12:32:38 -08:00
Ross Thompson
500e6ff430
Fixed buildroot to work with the fpga's merge.
2021-12-02 18:09:43 -06:00
Ross Thompson
a871118116
Merge branch 'main' into fpga
2021-11-29 10:10:37 -06:00
Ross Thompson
5642918ead
Merge branch 'main' into fpga
2021-11-29 10:06:53 -06:00
bbracker
fed0bb08d6
UART hack now looks at physical addresses so that it isn't bamboozled by S-mode accesses
2021-11-25 11:01:59 -08:00
bbracker
cffb72042a
activate STVAL for buildroot
2021-11-21 10:40:28 -08:00
Skylar Litz
6fde97b16c
fixed interrupt timing bug
2021-11-16 16:46:17 -08:00
bbracker
2203590f9f
get current privilege level from GDB for checkpoints
2021-11-15 14:49:00 -08:00
Skylar Litz
3dd83b3113
fix timing of delayed interrupt
2021-11-11 09:35:51 -08:00
bbracker
c92d41a597
checkpoint MIDELEG support
2021-11-06 03:44:23 -07:00
bbracker
bc6332a780
fix merge conflict
2021-11-05 23:42:15 -07:00
bbracker
17e776f853
checkpoints now use binary ram files
2021-11-05 22:37:05 -07:00
bbracker
0c7681b942
fix testbench interrupt timing
2021-11-02 21:19:12 -07:00
bbracker
66e53929ce
adapt testbench linux to use reset_ext
2021-10-25 13:26:44 -07:00
bbracker
8c4e6baf48
change CHECKPOINT to be a parameter (not a macro) so that do scripts can control it; clean up checkpoint initialization macros
2021-10-25 12:25:32 -07:00
bbracker
9b98a499d7
some linux testbench cleanup
2021-10-25 10:04:30 -07:00
bbracker
046a78a8fc
manually resolved git merge conflicts in testbench linux after checkpointing
2021-10-24 15:02:19 -07:00
bbracker
36b39358c6
add checkpointing to linux testbench
2021-10-24 06:47:35 -07:00
bbracker
26eead1c77
add W stage signals to linux testbench
2021-10-23 14:00:53 -07:00
bbracker
3c0b0987d2
add option for regression to do a partial execution of buildroot
2021-10-23 13:17:30 -07:00
Ross Thompson
de4ea16d32
Merge branch 'main' into fpga
2021-10-20 16:24:55 -05:00
bbracker
4abc6fc915
change infrastructure to expect only 6.3 million from buildroot
2021-10-12 10:41:15 -07:00
Ross Thompson
f6c6cb9ed2
Merge branch 'main' into fpga
2021-10-11 18:17:58 -05:00
bbracker
a88ae5aaff
use correct string formatting function
2021-10-10 10:09:59 -07:00
bbracker
6fce53d146
make testbench-linux halt on some discrepancies with QEMUw
2021-10-09 17:22:30 -07:00
Skylar Litz
5bcae393c9
added delayed MIP signal
2021-10-04 18:23:31 -04:00
bbracker
6aa79657ed
Revert "first attempt at verilog side of checkpoint functionality"
...
This reverts commit fec96218f6
2021-09-30 20:45:26 -04:00
bbracker
fec96218f6
first attempt at verilog side of checkpoint functionality
2021-09-28 23:17:58 -04:00
bbracker
7117c0493c
condense testbench code; debug_level of 0 means don't check at all
2021-09-27 03:03:11 -04:00
Ross Thompson
4d1b02c068
Merge branch 'main' into fpga
2021-09-26 13:22:53 -05:00
Ross Thompson
4f7bc1be48
Added either the sdModel or constant driver for the SDC ports in all test benches.
2021-09-24 12:31:51 -05:00
bbracker
3f96ff0ac0
switch testbench-linux's interrupts from xcause to mip and improve warning messages
2021-09-22 12:33:11 -04:00
bbracker
ff5379fd95
fix regression
2021-09-15 17:30:59 -04:00
Ross Thompson
6550f38af9
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-09-08 12:47:03 -05:00
bbracker
bb84354a47
fixed bug where M mode was sensitive to S mode traps
2021-09-07 19:14:39 -04:00
bbracker
f8272c45d1
make testbench successfully deactivate TimerIntM so as to create a nice pulse
2021-09-07 15:36:47 -04:00
bbracker
da9a366d20
No longer forcing CSRReadValM because that can feedback to corrupt some CSRs
2021-09-06 22:59:54 -04:00
bbracker
b3bc3cf6d0
modified testbench to not allow Wally to generate its own interrupts (because of fundamental interrupt imprecision limitations)
2021-09-04 19:49:26 -04:00
Ross Thompson
86fc632790
Moved data path logic from icacheCntrl to icache.
2021-08-26 10:58:19 -05:00
Ross Thompson
fe378f2692
Added function tracking to linux test bench.
2021-08-24 11:08:46 -05:00
Ross Thompson
c31b7b4dc5
Wally previously was overcounting retired instructions when they were flushed.
...
InstrValidM was used to control when the counter was updated. However this is
not suppress the counter when the instruction is flushed in the M stage.
2021-08-23 12:24:03 -05:00
Ross Thompson
2825074114
Confirmed David's changes to the interrupt code.
...
When a timer interrupt occurs it should be routed to the machine interrupt
pending MTIP even if MIDELEG[5] = 1 when the current privilege mode is
Machine. This is true for all the interrupts. The interrupt should not be
masked even though it is delegated to a lower privilege. Since the CPU
is currently in machine mode the interrupt must be taken if MIE.
Additionally added a new qemu script which pipes together all the parsing and
post processing scripts to produce the singular all.txt trace without the
massivie intermediate files.
2021-08-22 21:36:31 -05:00
