David Harris
d9e61fad67
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-25 06:37:30 -08:00
David Harris
9b491788b2
Checked in Chapter 2 C and assembly examples
2021-12-25 06:35:36 -08:00
Ross Thompson
d9977aa1f1
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-23 12:40:42 -06:00
Ross Thompson
7fe70c3cc6
Removed the fault state from the hptw. Now writing TLB faults into the I/DTLBs. This has two advantages.
...
1: It simplifies the interactions between the caches and the hptw.
2: instruction page faults are fetched 3 times, caching them in the ITLB speeds up this process.
There are two downsides.
1: Pollute the TLBs with not very relavent translations
2: Have to compute the misalignment. This can be cached in the TLB which only costs 1 flip flop
for each TLB line.
2021-12-23 12:40:22 -06:00
David Harris
a8c72c08a9
added wallyVirtIO.patch from Ross
2021-12-22 07:04:47 -08:00
Ross Thompson
4e1ae8c71f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-21 22:38:05 -06:00
Ross Thompson
f863bdc495
linux-wave.do changes.
2021-12-21 22:37:55 -06:00
David Harris
9ab7c18baa
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-22 03:59:14 +00:00
David Harris
b15707bb84
Fixed directory in Makefile for exe2memfile
2021-12-22 03:59:08 +00:00
Ross Thompson
6a8e917e06
It was possible for a load/store followed by tlb miss and update to have an exception and still commit its result to memory or register.
2021-12-21 15:59:56 -06:00
Ross Thompson
7844d3f064
Fixed bug where the wrong address is read into the icache memory.
2021-12-21 15:16:00 -06:00
Ross Thompson
8b97aaac3e
Fixed complex bug where FENCE is instruction class miss predicted as a taken branch.
2021-12-21 11:29:28 -06:00
Ross Thompson
3f62a64056
Identified bug in the IFU which selects PCNextF when InvalidateICacheM is true. If the ID is invalid PCNextF should NOT be PCE.
2021-12-20 23:45:55 -06:00
Ross Thompson
a157235a4b
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-20 23:27:46 -06:00
Ross Thompson
ffe792bcfc
Fixed bug on icache spill. if the cpu stalled on the completion it was possible to use the wrong address for the sram read. Also miss spill hit always selected the wrong address.
2021-12-20 23:27:37 -06:00
David Harris
b085339303
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-20 21:16:25 -08:00
David Harris
07810f4025
Renamed to setup.sh and fixed path bug
2021-12-20 21:14:35 -08:00
David Harris
e00791a890
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-21 05:10:17 +00:00
David Harris
09a24f7240
Improving Wally installation makefile
2021-12-21 05:10:14 +00:00
David Harris
bf9082b0ad
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-20 21:09:20 -08:00
David Harris
475fa01767
Fixing paths in wally-setup.sh
2021-12-20 21:08:34 -08:00
Ross Thompson
6acf6257e4
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-20 21:26:48 -06:00
Ross Thompson
50b307bc0e
Looks like rdtime was accidentally replaced with rrame from a find and replace.
2021-12-20 21:26:38 -06:00
David Harris
972841717f
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-21 02:35:45 +00:00
David Harris
787af4287e
Removed riscv-isa-sim submodule from Wally; use it in /opt/riscv instead
2021-12-21 02:35:41 +00:00
Ross Thompson
8416cae3fe
Fixed Type 5b interaction between dcache and hptw.
...
This is a load concurrent with ITLBMiss.
2021-12-20 18:33:31 -06:00
Ross Thompson
b6d75d453a
Modified LSU verilog is compatible with vivado. have to use extra logic IEUAdrExtM.
2021-12-20 10:03:56 -06:00
Ross Thompson
beb1988539
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-20 10:03:19 -06:00
Ross Thompson
df8bd78679
More signal name cleanup in LSU.
2021-12-19 22:47:48 -06:00
Ross Thompson
3eb5f33705
Remove verbosity from lsu state machine.
2021-12-19 22:41:34 -06:00
Ross Thompson
d3c3422d12
Rename of SelPTW to SelHPTW.
2021-12-19 22:24:07 -06:00
Ross Thompson
8feb36b926
Signal renames.
2021-12-19 22:21:03 -06:00
Ross Thompson
dc82d44f9e
Hardware reductions in the lsu.
2021-12-19 22:00:28 -06:00
Ross Thompson
dc95896303
Removed HPTWStall. Not needed as InterlockStall from the LSU provides the equivalent.
2021-12-19 21:36:54 -06:00
Ross Thompson
138da1fefa
Removed lsuArb and placed remaining logic in lsu.sv.
...
Removed after itlb walk signal as the dcache no longer has any need for this.
Formated lsu.sv
2021-12-19 21:34:40 -06:00
Ross Thompson
cc5c5da8bc
Added file showing how to compile riscv toolchain for different extension combinations.
2021-12-19 20:31:55 -06:00
Ross Thompson
596cc4fde4
Moved convert2bin.py to the tests directory. This file converts the qemu ram.txt output into a binary for copy to flash card.
...
mv qemu patches to tests directory.
2021-12-19 20:11:32 -06:00
David Harris
a25d541dcf
Moved generate of conditional units to hart
2021-12-19 17:03:57 -08:00
David Harris
3c3bfd055e
Moved generate statements for optional units into wallypipelinedhart
2021-12-19 16:53:41 -08:00
Ross Thompson
d9cc9afd49
Changes to buildroot to support MemAdrM to IEUAdrM name changes.
2021-12-19 18:24:40 -06:00
Ross Thompson
32a4afc7a1
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-19 18:16:49 -06:00
Ross Thompson
a39b47d226
Switched to using an always block for lsu stall logic. This avoids the problematic x propagation.
2021-12-19 18:16:08 -06:00
Ross Thompson
eceb418056
Implemented what I think is the last required change for the lsu state machine.
2021-12-19 17:57:12 -06:00
Ross Thompson
fe5c05eb8d
Created hack to get around imperas64mmu unknown (value = x) bug.
2021-12-19 17:53:13 -06:00
Ross Thompson
c453b285dc
Fixed bug where icache did not replay PCF on itlb miss.
2021-12-19 17:01:13 -06:00
Ross Thompson
c9291655da
Fixed bug most of the bugs related to the dcache changes, but the mmu tests don't pass.
2021-12-19 16:12:31 -06:00
David Harris
53cd2ac049
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-19 13:53:53 -08:00
David Harris
9e6c9c38c0
ALUControl cleanup
2021-12-19 13:53:45 -08:00
Katherine Parry
e3f2a252cd
fixed some small errors in FMA
2021-12-19 13:51:46 -08:00
Ross Thompson
f4d778c2f6
Corrected the LSU's fsm for stalling CPU. Removed state from hptw fsm.
2021-12-19 15:10:33 -06:00
