Thomas Fleming
d8ac9034b7
Create virtual memory ad-hoc test
...
Test program is currently failing on ovpsim. There is no indication that ovpsim
is properly implementing virtual memory translation when satp is set accordingly.
Need to confirm whether this is a problem with ovpsim, how ovpsim is being
called, or the test itself.
2021-03-03 17:06:37 -05:00
Teo Ene
4562c61af3
Fix to last push
2021-03-03 15:20:38 -06:00
Teo Ene
37bf3d836f
Updated coremark .do file for easier debugging
2021-03-03 15:10:39 -06:00
Teo Ene
e6044b9867
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-03-02 17:23:44 -06:00
Teo Ene
e7f7f980b3
Updated coremark .do file for easier debugging
2021-03-02 17:23:39 -06:00
David Harris
9bcddfa5dd
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-01 00:09:55 -05:00
David Harris
2543c29839
Initial (untested) implementation of lr and sc
2021-03-01 00:09:45 -05:00
Teo Ene
babe6ce9db
Properly implemented the fix from commit 31c07b2adc
2021-02-28 22:22:04 -06:00
Noah Boorstin
1858c32e9d
add .nfs* files to gitignore
2021-02-28 20:48:01 +00:00
David Harris
cf03afa880
Eliminated flushing pipeline on CSR reads
2021-02-26 17:00:07 -05:00
David Harris
015b632eb1
Cleaned out unused signals
2021-02-26 09:17:36 -05:00
David Harris
b16846bddb
Clean up bus interface code
2021-02-26 01:03:47 -05:00
David Harris
24f767a404
Retimed peripherals for AHB interface
2021-02-26 00:55:41 -05:00
Brett Mathis
4e6caf64d9
Fcmp/Fsgn pipeline modules
2021-02-25 18:22:30 -06:00
David Harris
c060e427f0
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-02-25 15:49:38 -05:00
David Harris
a16fd95eed
Restored to working multiplier after Lab 2
2021-02-25 15:32:43 -05:00
Brett Mathis
ec82453ba1
FPU Assembly tests
2021-02-25 14:32:36 -06:00
Teo Ene
6be5bb1f84
Fixed previous commit
2021-02-25 11:24:44 -06:00
Teo Ene
31c07b2adc
Edited imem to account for TIMBASE==0; still hard-coded and needs to be improved, but works with coremark config now.
2021-02-25 11:23:01 -06:00
Teo Ene
61b872a3e8
Changed TIMBASE in coremark config file
2021-02-25 11:03:41 -06:00
Teo Ene
544df9e18c
Merge remote-tracking branch 'origin/lab3' into main
2021-02-25 10:28:20 -06:00
Teo Ene
c47872c2af
Changed .do file back to run all
2021-02-25 09:58:54 -06:00
David Harris
d00d42cf9a
Merged bus into main
2021-02-25 00:28:41 -05:00
David Harris
3b6807368f
removed WALLY ALU tests to avoid merge conflict with main branch
2021-02-25 00:15:22 -05:00
Teo Ene
3e5de35fc4
Added provisional coremark files from work with Elizabeth
2021-02-24 20:07:07 -06:00
David Harris
f5e9c91193
All tests passing with bus interface
2021-02-24 07:25:03 -05:00
Katherine Parry
8f5cc19143
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-02-23 20:21:53 +00:00
Katherine Parry
7b103423e1
inital FMA push
2021-02-23 20:19:12 +00:00
David Harris
c52a99ce2d
Fixed fetch stall after jump in bus unit
2021-02-23 09:08:57 -05:00
David Harris
817f81c356
Debugging Bus interface
2021-02-22 13:48:30 -05:00
David Harris
acd7ba8b60
Updated creation date of mul
2021-02-18 08:13:08 -05:00
David Harris
2f5b4c3a25
Resotred part of multiplier for lab 2
2021-02-17 16:14:04 -05:00
David Harris
64536dbc34
Removed multiplier for lab 2
2021-02-17 16:06:16 -05:00
David Harris
dc758a0c7b
Multiplier tweaks
2021-02-17 16:00:27 -05:00
David Harris
3edf910c18
Started to integrate OSU divider
2021-02-17 15:38:44 -05:00
David Harris
cb0054b524
Multiply instructions working
2021-02-17 15:29:20 -05:00
David Harris
8dec69c2ce
Added MUL
2021-02-15 22:27:35 -05:00
Teo Ene
a842879741
Added scripts to report power and area on a module-by-module basis
2021-02-15 12:09:33 -06:00
David Harris
f00728448a
WALLY ALU tests
2021-02-15 10:16:31 -05:00
David Harris
f6ec4a4548
Makefrag for ALU testsgen
2021-02-15 10:12:24 -05:00
David Harris
37dba8fd26
More memory interface, ALU testgen
2021-02-15 10:10:50 -05:00
Domenico Ottolia
75d9091fe8
Add privileged test cases
2021-02-14 17:01:46 -05:00
Teo Ene
dba5ce9c8b
Due to legacy code, make pnr would print out an internal Makefile error at the end of the run. While this error was inconsequential and did not affect anything, it still needed to be removed.
2021-02-14 13:43:30 -06:00
Teo Ene
72dd97d9b6
sky130 18T and 15T cell libraries removed
...
Upon noticing their size, concerns were raised about available drive space.
As 12T is the main implementation focus, the decision was made to remove 15T and 18T.
Apologies if any were interested in implementing the processor across multiple standard cell libraries for comparison.
2021-02-14 09:05:41 -06:00
Teo Ene
e878a8bed2
After conferring with Dr. Harris, removed riscv-o3 submodule that most contributors to this repository lack access to.
2021-02-14 08:58:33 -06:00
Teo Ene
f3c902450b
After going through Lab 3 again, I've decided to make small changes to the provided floorplan so that it may serve as a slighly better example of a good floorplan.
2021-02-14 04:43:07 -06:00
Teo Ene
da6e9730a0
Cleaning up my code a little bit more
2021-02-14 02:58:25 -06:00
Teo Ene
83f7cd51e5
Final changes to the lab3 branch
...
- Removed manual register file placement script, as it has been removed from lab.
- Created pre-sets that only have to be uncommented for the changing clock target portion of lab.
- Cleaned up Makefile in case anyone looks inside of it.
2021-02-14 02:01:20 -06:00
Teo Ene
86fa5210f3
Commiting sample floorplan that I failed to commit last night
2021-02-13 12:08:03 -06:00
Teo Ene
ca7ee1d670
- Cleaned up unnecessary files
...
- Pulled updates for std cells
- Fixed typo that prevented easy switching between standard cell variants
- Fixed asynchronous reset paths from not being flagged as false
2021-02-12 21:49:42 -06:00
