Thomas Fleming 19ac77d3fa Fix compiler warning in PMP checker		2021-05-04 15:18:08 -04:00
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csr.sv	Implement PMP checker and revise PMA checker	2021-05-03 17:37:42 -04:00
csrc.sv	Merge branch 'tests' into icache-almost-working	2021-04-25 21:25:36 -05:00
csri.sv	Merge branch 'tests' into icache-almost-working	2021-04-25 21:25:36 -05:00
csrm.sv	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-05-03 23:15:39 -04:00
csrn.sv	Fix bug that caused stvec to get the wrong value	2021-05-03 17:54:57 -04:00
csrs.sv	Fix bug that caused stvec to get the wrong value	2021-05-03 17:54:57 -04:00
csrsr.sv	Clean up PMA checker and begin PMP checker	2021-04-29 02:20:39 -04:00
csru.sv	Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.	2021-03-30 23:18:20 -05:00
pmachecker.sv	Adjust attributes in PMA checker	2021-05-03 21:58:32 -04:00
pmpadrdec.sv	Disable PMP checker to fix test loops	2021-05-04 01:56:05 -04:00
pmpchecker.sv	Fix compiler warning in PMP checker	2021-05-04 15:18:08 -04:00
privdec.sv	Fix bug with IllegalInstrFaultM not getting correct value	2021-05-03 22:48:03 -04:00
privileged.sv	Implement PMP checker and revise PMA checker	2021-05-03 17:37:42 -04:00
trap.sv	Make vectored interrupt trap handling work, and add tests for mtvec with vectored interrupts	2021-04-29 20:42:14 -04:00