slmnemo
|
d291387b81
|
added individual makes for arch and wally tests as well as memfiles to Makefile. run using make archtests/wallytests/memfiles
|
2022-06-21 15:54:24 -07:00 |
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Katherine Parry
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e9f5778e2a
|
using memread for quotent select
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2022-06-21 15:49:52 -07:00 |
|
Katherine Parry
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c41391e228
|
removed rv64fp from lint
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2022-06-21 15:48:47 -07:00 |
|
David Harris
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8537b883d1
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-06-21 22:45:28 +00:00 |
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Daniel Torres
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cf56a0d76a
|
fixed issue where the unused spike elf files were being used to find objdump files that didn't exist causing makefile-memfile to fail prematurely
|
2022-06-21 15:39:04 -07:00 |
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Madeleine Masser-Frye
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0161683945
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-06-21 20:31:06 +00:00 |
|
Madeleine Masser-Frye
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fe31ee92e8
|
switched comparator to dc flip version
|
2022-06-21 20:30:33 +00:00 |
|
James Stine
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493d3b1ac0
|
Add hex output in bad but okay way
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2022-06-21 15:07:24 -05:00 |
|
James Stine
|
8e177b02e4
|
Add MATLAB scripts for PD plot
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2022-06-21 10:14:53 -05:00 |
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slmnemo
|
2b2760f5bd
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-06-21 02:16:26 -07:00 |
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slmnemo
|
2b2ddbcc5e
|
Added rudimentary GPIO test according to testplans in chapter 15
|
2022-06-21 02:16:21 -07:00 |
|
Katherine Parry
|
edc15d6ef9
|
made fixes to radix-2 divider testbench - divider doesn't pass
|
2022-06-20 23:01:53 +00:00 |
|
Katherine Parry
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5d5f79eb8f
|
radix-4 divider passing tests
|
2022-06-20 22:56:08 +00:00 |
|
Katherine Parry
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254ebf478e
|
added fld in rv32 - needs testing
|
2022-06-20 22:53:13 +00:00 |
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James Stine
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1108268557
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Update C program for r=4 division by recurrence to match Table in EL
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2022-06-20 11:32:40 -05:00 |
|
Daniel Torres
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d077199608
|
embench and testbench now support running both O2 and Os build variations without overwriting one another
|
2022-06-17 21:15:42 -07:00 |
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Daniel Torres
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1ef5ed8005
|
arch tests now run on spike and sail and compare signatures during build
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2022-06-17 20:53:15 -07:00 |
|
Daniel Torres
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dcdd3702c3
|
removed old code from makefile, simplified code in testbench
|
2022-06-17 15:13:38 -07:00 |
|
Daniel Torres
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3a5c02b44a
|
arch bug fixes and testbench changes
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2022-06-17 15:07:16 -07:00 |
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David Harris
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7e4988c2de
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-17 15:45:24 +00:00 |
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Katherine Parry
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8425f8838d
|
hopefully fixed lint error
|
2022-06-17 00:14:39 +00:00 |
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Katherine Parry
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93906b9457
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-15 22:58:42 +00:00 |
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Katherine Parry
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e121dcd4af
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postprocess out of fpu critical path
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2022-06-15 22:58:33 +00:00 |
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Madeleine Masser-Frye
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c2493168b6
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-06-15 18:30:27 +00:00 |
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Madeleine Masser-Frye
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76e30ed8ab
|
cleanup, plots for paper
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2022-06-15 18:28:36 +00:00 |
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James Stine
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d69a8f4077
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Add back SV for integer division to use 8-bit CPA in qslc
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2022-06-15 11:46:39 -05:00 |
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James Stine
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535a9a04ee
|
Add r=4 C code
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2022-06-15 11:44:09 -05:00 |
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Katherine Parry
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11b252a735
|
some synth fpu optimizations
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2022-06-14 23:58:39 +00:00 |
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David Harris
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ecd733942a
|
Removed testbench.sv.bak
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2022-06-14 22:04:38 +00:00 |
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Katherine Parry
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998876ce49
|
removed false critical path from fpu
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2022-06-14 16:50:46 +00:00 |
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Katherine Parry
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566001e07b
|
fixed acciedental critical path in FPU
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2022-06-14 00:02:38 +00:00 |
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DTowersM
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919c1818a8
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-13 23:34:35 +00:00 |
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DTowersM
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1f4d56ba32
|
added back working coremark in benchmarks/riscv64-bcoremarkdirectory, experimental simplifications are in benchmarkscoremark/ but this doesn't currently work (some type of c bug)
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2022-06-13 23:23:57 +00:00 |
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Katherine Parry
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31fd8772cf
|
postprocessing unit created and passing all tests
|
2022-06-13 22:47:51 +00:00 |
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David Harris
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8ea484a343
|
Cleanup on RAM module
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2022-06-13 19:37:43 +00:00 |
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David Harris
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b7a7ca6eac
|
Typo in gpio reset
|
2022-06-13 19:37:05 +00:00 |
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slmnemo
|
eb41185a70
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-06-13 12:30:33 -07:00 |
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David Harris
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be65e8f862
|
Removed SRT testvectors from repo
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2022-06-13 19:27:33 +00:00 |
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slmnemo
|
915b8e2adb
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-06-13 12:27:23 -07:00 |
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slmnemo
|
7b704f8db0
|
Merge branch 'cacheburstmode' into main.
Cache burst mode is now working! It also uses the new RAM.
|
2022-06-13 12:26:18 -07:00 |
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slmnemo
|
98c07ce2c0
|
Added more comments
|
2022-06-13 12:26:08 -07:00 |
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David Harris
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ccd16210bc
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-13 19:26:07 +00:00 |
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David Harris
|
e9ef9a5cb8
|
Fixed XOR logic in GPIO
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2022-06-13 19:26:03 +00:00 |
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slmnemo
|
3d715a098c
|
Added comment about name of LSUBusInit/Lock signal
|
2022-06-13 10:56:02 -07:00 |
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slmnemo
|
cadd62e49f
|
Removed irrelevant comments in ahblite and made it more clear when to use certain transmission signals
|
2022-06-10 20:43:56 -07:00 |
|
slmnemo
|
beb4317e68
|
Added comments to signals added so the bus is easier to analyze
|
2022-06-10 20:30:04 -07:00 |
|
slmnemo
|
b7357efc6b
|
Fixed failed regression state by only enabling counting when doing cached operations
|
2022-06-10 20:00:09 -07:00 |
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slmnemo
|
63ed390c90
|
Fixed error where CntReset would be high one cycle too long, adding a cycle of delay. Broke wally64priv by failing trap-sret-01.
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2022-06-10 19:10:01 -07:00 |
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Madeleine Masser-Frye
|
422bd2043f
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-06-10 21:11:47 +00:00 |
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Madeleine Masser-Frye
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7cdf9cd4d3
|
added 'd' suffix to muxes for data-critical synths
|
2022-06-10 21:11:05 +00:00 |
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DTowersM
|
4bbe5eeecd
|
simplified coremark
|
2022-06-10 19:15:17 +00:00 |
|
slmnemo
|
dc11066ff2
|
Passed Regression: Seems to work perfectly fine
|
2022-06-09 18:21:13 -07:00 |
|
slmnemo
|
ec7cdee0f3
|
Merge branch 'main' into cacheburstmode
|
2022-06-09 17:51:03 -07:00 |
|
slmnemo
|
5a6eae214a
|
?
|
2022-06-09 17:50:47 -07:00 |
|
DTowersM
|
9e2d80764d
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-10 00:38:07 +00:00 |
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DTowersM
|
dd34f25ffd
|
changed DCACHE_LINELENINBITS and ICACHE_LINELENINBITS to 512, had to modigy the wfi test to increase timee before interupt to mantain compatability
|
2022-06-10 00:37:53 +00:00 |
|
slmnemo
|
3e8d3bae88
|
Changes made on 9th Jun
|
2022-06-09 17:33:51 -07:00 |
|
slmnemo
|
4ff105f18c
|
Fixed lint error
|
2022-06-09 17:22:04 -07:00 |
|
David Harris
|
c836f37a08
|
New RAM for further testing
|
2022-06-09 23:50:43 +00:00 |
|
stineje
|
470c0552f8
|
Update integer division for r4 and qslc_r4a2.c
|
2022-06-09 16:45:13 -05:00 |
|
David Harris
|
dd4fa7c682
|
qslc_r4a2 generator
|
2022-06-09 17:26:47 +00:00 |
|
slmnemo
|
0d04751c77
|
Fixed error when doing uncached accesses where HTRANS was always 2
|
2022-06-08 18:58:07 -07:00 |
|
slmnemo
|
81d373c7ab
|
Fixed error related to bus being unable to complete a line write after a memory read followed by an idle and cachewrite request.
|
2022-06-08 17:34:02 -07:00 |
|
Madeleine Masser-Frye
|
0e64494e46
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-06-09 00:08:15 +00:00 |
|
Madeleine Masser-Frye
|
a58a756076
|
added one bit muxes for data critical synths
|
2022-06-09 00:06:12 +00:00 |
|
slmnemo
|
11924bdd9b
|
Fixed error where MEMREAD would go into INSTRREAD even when no INSTRREAD was pending
|
2022-06-08 15:59:15 -07:00 |
|
slmnemo
|
e17ee3073e
|
Fixed ifu displaying LSU bus state in wave.do
|
2022-06-08 15:30:32 -07:00 |
|
slmnemo
|
315c2f0669
|
Working version: Fixed error where Word count would always increment even without AHB to bus ACK
|
2022-06-08 15:29:32 -07:00 |
|
slmnemo
|
054cf5f7b0
|
Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors
|
2022-06-08 15:03:15 -07:00 |
|
DTowersM
|
6402b2dec4
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-08 16:28:18 +00:00 |
|
DTowersM
|
6944996329
|
added #1 delays to Stalls and Flushes in hazard unit
|
2022-06-08 16:28:09 +00:00 |
|
slmnemo
|
284e0395a0
|
Merge branch 'main' into cacheburstmode
|
2022-06-08 02:21:33 +00:00 |
|
slmnemo
|
2d76953d42
|
Added lock signal to ensure AHB speaks with the right bus
|
2022-06-08 02:19:21 +00:00 |
|
David Harris
|
5240bd1c90
|
Modified RAM for single-cycle latency
|
2022-06-08 02:06:00 +00:00 |
|
David Harris
|
3c8eafc8ee
|
Cleaned bram interface
|
2022-06-08 01:39:44 +00:00 |
|
David Harris
|
9e5ab4d378
|
Added ahbapbbridge and cleaning RAM
|
2022-06-08 01:31:34 +00:00 |
|
DTowersM
|
a190342b8a
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-07 23:58:58 +00:00 |
|
DTowersM
|
02a424d65b
|
modified testbench.sv- now works with coremark
|
2022-06-07 23:58:50 +00:00 |
|
DTowersM
|
e324db71b4
|
cleaned up the <begin_signature> code, now works for code bases larger than 0x10000000
|
2022-06-07 23:27:54 +00:00 |
|
slmnemo
|
6d36150c3d
|
Fixed off-by-one error in busdp capture
|
2022-06-07 19:36:39 +00:00 |
|
slmnemo
|
73e0c1c07f
|
Reworked bus to handle burst interfacing
|
2022-06-07 11:22:53 +00:00 |
|
DTowersM
|
df330961b8
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-07 06:03:19 +00:00 |
|
DTowersM
|
590cf243bb
|
added support for 64 bit rv tests
|
2022-06-07 06:02:23 +00:00 |
|
Katherine Parry
|
cfcaddf8aa
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-06 16:06:54 +00:00 |
|
Katherine Parry
|
8fa0fc4229
|
fma synth warnings and errors removed
|
2022-06-06 16:06:04 +00:00 |
|
slmnemo
|
7f70655113
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-06-03 18:56:29 -07:00 |
|
slmnemo
|
3fe78c9084
|
Fixed recurrent issue with testbench where it would never stop
|
2022-06-03 18:56:24 -07:00 |
|
cturek
|
afdfe770fc
|
Added integer division in srt, parametrized everything to work with integers and floating points, parametrized testbench.
|
2022-06-04 00:14:10 +00:00 |
|
DTowersM
|
caaf56cbf7
|
testbench now reads begin_signature addr from .objdump.addr instead of from tests.vh
|
2022-06-03 22:07:14 +00:00 |
|
Madeleine Masser-Frye
|
56a053fc3d
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-06-03 21:08:49 +00:00 |
|
Madeleine Masser-Frye
|
31e9d0a41a
|
added muxes and inv, fixed priority encoder
|
2022-06-03 21:03:13 +00:00 |
|
Katherine Parry
|
fd980fe9d6
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-03 15:34:27 +00:00 |
|
Katherine Parry
|
6b39b8c702
|
fixed compilation errors
|
2022-06-03 15:34:17 +00:00 |
|
slmnemo
|
9d1dfbdb50
|
Changed NO_SPOOFING from 0 to 1 in buildroot-no-trace to better facilitate wally booting linux without following QEMU's trace
|
2022-06-03 04:55:14 -07:00 |
|
Katherine Parry
|
8420b1e87c
|
removed some debuging code accedentally pushed
|
2022-06-02 22:45:19 +00:00 |
|
Katherine Parry
|
6a4502e987
|
added rv64fpquad
|
2022-06-02 22:10:00 +00:00 |
|
Katherine Parry
|
cd8b2a2b98
|
added config rv64fpquad
|
2022-06-02 22:09:11 +00:00 |
|
David Harris
|
c74fec7fa6
|
renamed sim-fp to sim-testfloat
|
2022-06-02 15:05:29 -07:00 |
|
Katherine Parry
|
03280c0f9c
|
added createallvectors
|
2022-06-02 21:56:05 +00:00 |
|
slmnemo
|
c8515001a2
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-06-02 12:54:08 -07:00 |
|