Ross Thompson
9b3637bd87
RAS needs to be reset or preloaded. For now I just reset it.
...
Fixed bug with the instruction class.
Most tests now pass. Only Wally-JAL and the compressed instruction tests fail. Currently the bpred does not support compressed. This will be in the next version.
2021-02-19 20:09:07 -06:00
Ross Thompson
00de91cc87
Added FlushF to hazard unit.
...
Fixed some typos with the names of signals in the branch predictor. They were causing signals to be not set. Note there is a modelsim flag which prevents it from compiling if a logic is undefined.
I will look this up and add it to the compiler.
2021-02-19 16:36:51 -06:00
Ross Thompson
c6ebe7733b
Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary.
...
About 149307ns of simulation run.
2021-02-18 21:32:15 -06:00
Ross Thompson
5df7e959f3
Integrated the branch predictor into the hardward. Not yet working.
2021-02-17 22:19:17 -06:00
Ross Thompson
78db3654c6
We now have a solid rough draft of the 2 bit sat counter branch predictor with BTB and RAS.
...
This is not yet tested but the system verilog does compile.
2021-02-15 14:51:39 -06:00
Ross Thompson
3ec1f668fc
added branch predictor 2 bit table + SRAM model. The SRAM model is only approximate, but it does correctly model the read and write pipelined behavior.
2021-02-14 15:13:55 -06:00
Ross Thompson
30df1cdd25
The top level of the branch predictor built and compiles. Does not yet function. Missing the BTB, RAS, and direction prediction tables.
2021-02-14 11:06:31 -06:00
bbracker
9231646fb3
bus rw bugfix and peripherals testing
2021-02-12 00:02:45 -05:00
Brett Mathis
79cb7ed571
Parallel FSR's and F CTRL logic
2021-02-04 02:25:55 -06:00
David Harris
91f6858de7
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-02-02 19:44:43 -05:00
David Harris
a44c2abb12
Minor tweaks
2021-02-02 19:44:37 -05:00
Noah Boorstin
00d9e13d68
same thing but do that right this time
2021-02-02 21:47:15 +00:00
Noah Boorstin
56ff32f857
change undefined syntax in extend.sv
...
don't need verilator execption anymore
2021-02-02 21:39:20 +00:00
David Harris
d56d7a75a6
Rename ifu/dmem/ebu signals to match uarch diagram
2021-02-02 15:09:24 -05:00
David Harris
aee44bb343
Changed DTIM latency to 2 cycles
2021-02-02 14:22:12 -05:00
David Harris
4fbb5f0f1b
Cleaned up hazard interface
2021-02-02 13:53:13 -05:00
David Harris
c23afbda3a
Moved LoadStall generation to IEU
2021-02-02 13:42:23 -05:00
David Harris
aad1d3d7dd
Moved writeback pipeline registers from datapth into DMEM and CSR
2021-02-02 13:02:31 -05:00
David Harris
9d7e242596
Moved fpu to temporary location to fix compile and cleaned up interface formatting
2021-02-01 23:44:41 -05:00
Brett Mathis
94de3e9fb2
OSU FPU IP initial commit
2021-02-01 19:33:43 -06:00
David Harris
056b147b13
Renamed DCU to DMEM
2021-02-01 18:52:22 -05:00
David Harris
396cea1ea7
Reorganized src hierarchically
2021-01-30 11:50:37 -05:00
David Harris
fc1fb94217
Working on reading instruction from TIM
2021-01-30 01:57:51 -05:00
David Harris
61fd7c4499
Adding stalls for memory delays
2021-01-30 01:43:49 -05:00
David Harris
9c81278f28
Added HCLK and HRESETn
2021-01-30 00:56:12 -05:00
David Harris
a357f2a0e7
Connected AHB bus to Uncore
2021-01-29 23:43:48 -05:00
David Harris
73a584b223
Added SATP, PMPCFG0-3, PMPADDR0 CSRs for Linux team
2021-01-29 18:06:36 -05:00
David Harris
e700e404c9
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-29 17:29:01 -05:00
David Harris
9a51bb27c3
Implemented adrdec for uncore
2021-01-29 17:28:53 -05:00
Teo Ene
9eafdbe349
- Removed latch on CSRCReadValM in csrc.sv
...
- Changed top level to wallypipelinedhart
2021-01-29 15:56:51 -06:00
David Harris
dc2443c55b
Moving data memory to uncore
2021-01-29 15:37:51 -05:00
David Harris
ed3cb83c10
Added ahblite bus interface unit
2021-01-29 01:07:17 -05:00
David Harris
618c6e4813
Renamed modules in privileged unit
2021-01-28 23:21:12 -05:00
David Harris
05b755958f
Hint to optimize ifu
2021-01-28 21:40:48 -05:00
David Harris
fe0876027f
Fixed floating signals in clint and ieu
2021-01-28 15:44:05 -05:00
David Harris
ad5d4793b6
Fixed c.jr instruction improperly writing ra
2021-01-28 15:18:23 -05:00
David Harris
f95d0690ca
Created DCU and moved memdp into DCU
2021-01-28 01:03:12 -05:00
David Harris
a50b6c2a15
Provided PC + 2 or 4 (PCLink) for JAL
2021-01-28 00:22:05 -05:00
David Harris
824014c5c0
Repartitioned with Instruction Fetch Unit, Integer Execution Unit
2021-01-27 22:49:47 -05:00
David Harris
616afaba69
Moved privileged unit from datapath to hart
2021-01-27 07:46:52 -05:00
David Harris
b88508ca11
Repartitioned datapath and controller into ieu
2021-01-27 06:40:26 -05:00
David Harris
1d9c741c00
Reset Vector moved to config file
2021-01-25 15:57:36 -05:00
David Harris
fa18052348
Added test configurations
2021-01-25 11:28:43 -05:00
Noah Boorstin
aea1c0cd2e
small busybear testbench changes
2021-01-24 20:43:47 -05:00
Noah Boorstin
e7288716f7
Linux testbench works now
...
Added parameterized PCSTART to allow compatibility between imperas and busybear tests
Hopefully we are done with the "busybear" branch, please don't use it for future work
2021-01-24 17:10:00 -05:00
Noah Boorstin
12a8f83025
Merge branch 'busybear' into main
...
Merging busybear testbench into main, keeping main edits of wally src
2021-01-24 16:28:36 -05:00
Noah Boorstin
b08b86f561
sucessfully simulate first 30 instructions
...
still need to find a better solution to InstrAccessFault/DataAccessFault though
2021-01-23 19:01:44 -05:00
Noah Boorstin
a75d7e4555
More linux testbench fixes
...
So I'm super sorry for accidently overwriting the commits this morning
Need to be more careful with force pushing :(
This fixes the problem with CSRR somehow, by tying InstrAccessFaultF and
DataAccessFaultM to zero for now. I feel like this is not a good solution
and will cause problems in the future, but for the start it seems to work for now.
I'm fair certain we need these to accurately simulate to do linux properly.
Anyway, this super hackish solution is in place for now, now on to ignoring mispredicted reads
2021-01-23 17:52:05 -05:00
Noah Boorstin
be62987dec
Linux test now gets through first 8 instructions!
...
fixes the python parser:
get the value, not function name, of PC
only write changes to registers instead of registers every cycle
temporarilly NOP out CSRR instruction (with the canonical NOP), that was breaking this
dont stop on errors, print them prettier
2021-01-23 16:46:45 -05:00
David Harris
3905e77e54
Replaced parameters with macros for XLEN, MISA, other configuration, and renamed wally-params.sv to wally-config.vh
2021-01-23 10:48:12 -05:00
