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1973 Commits

Author SHA1 Message Date
Ross Thompson
4daeb6657f Merge branch 'tlb_fixes' into main 2021-12-18 12:24:17 -06:00
David Harris
7e026f3e78 Simplified Shifter Right input 2021-12-18 10:21:17 -08:00
David Harris
27ec8ff893 Shared ALU mux input for shifts 2021-12-18 10:08:52 -08:00
David Harris
eed2765033 Factored out common parts of shifter 2021-12-18 10:01:12 -08:00
David Harris
53baf3e787 Cleaning shifter 2021-12-18 09:43:09 -08:00
David Harris
ebcffcdebd Moved W64 truncation after result mux 2021-12-18 09:27:25 -08:00
David Harris
23c6b6370f Forwarding logic factoring 2021-12-18 05:40:38 -08:00
David Harris
10dfefa8ad Simplified FWriteInt interfaces by merging into RegWrite 2021-12-18 05:36:32 -08:00
David Harris
0f319b45c1 Do File cleanups 2021-12-17 17:45:26 -08:00
Ross Thompson
bbd1332353 Merge remote-tracking branch 'origin/tlb_fixes' into main 2021-12-17 14:40:29 -06:00
Ross Thompson
a11597b6bd Added more debugging code for FPGA. 2021-12-17 14:40:25 -06:00
Ross Thompson
ee81cfff0c Possible fix for icache deadlock interaction with hptw. 2021-12-17 14:38:25 -06:00
David Harris
aebd746e71 Renamed MemAdrE to IEUAdrE and moved the MemAdrM flop from IEU to LSU to reduce wires crossing hierarchies 2021-12-15 12:10:45 -08:00
David Harris
4e35736e90 IEU cleanup: 2021-12-15 11:38:26 -08:00
Ross Thompson
6d2a4b8354 Oups missed files in the last commit. 2021-12-15 10:25:08 -06:00
David Harris
865d5ce0b1 Renamed dtim->ram and boottim ->bootrom 2021-12-14 13:43:06 -08:00
David Harris
d7e78f8707 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-14 13:05:47 -08:00
David Harris
ecce1e62ee changed ideal memory to MEM_DTIM and MEM_ITIM 2021-12-14 13:05:32 -08:00
Ross Thompson
9886ed3028 Comments for dcache and icache refactoring. 2021-12-14 14:46:29 -06:00
David Harris
8dcf2c65f2 renamed rv32/64g to rv32/64gc in configuration 2021-12-14 11:22:00 -08:00
David Harris
0e9fe6c214 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-14 11:15:58 -08:00
David Harris
2d24230093 ALU and datapath cleanup 2021-12-14 11:15:47 -08:00
Ross Thompson
997a733a97 Added patch file for the qemu modifications. 
Added instructions for building and installing qemu.
 2021-12-13 18:36:00 -06:00
Ross Thompson
af9f97454d Cleaned up fpga synthesis script. 2021-12-13 18:26:54 -06:00
Ross Thompson
2d662bc4be Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-13 17:16:20 -06:00
Ross Thompson
81da8b8d2a Formating changes to cache fsms. 2021-12-13 17:16:13 -06:00
Ross Thompson
4d6d72a082 Fixed some typos in the dcache ptw interaction documentation. 2021-12-13 15:47:20 -06:00
David Harris
55f3979b67 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-13 07:57:49 -08:00
David Harris
2039752740 Simplified ALU and source multiplexers pass tests 2021-12-13 07:57:38 -08:00
kwan
8f79a12cbb priviledge .* removed, passed regression 2021-12-13 00:34:43 -08:00
kwan
f0e425e4ea test 2021-12-13 00:31:51 -08:00
kwan
a365e86197 priviledge .* fixed, passed local regression 2021-12-13 00:22:01 -08:00
Kevin
03274de97c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-12 17:53:41 -08:00
Kevin
98420cb988 dot stars conversions on the rest of the testbenches 2021-12-12 17:53:26 -08:00
Ross Thompson
051dd7d09d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-12 17:33:29 -06:00
Ross Thompson
395766219b Revert "Privilige .*s removed" 
This reverts commit 82bab8e90e.
 2021-12-12 17:31:57 -06:00
Ross Thompson
f758a53247 Revert "Priviledged .* removed" 
This reverts commit a95efea0b3.
 2021-12-12 17:31:39 -06:00
Ross Thompson
39168a201b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-12 17:21:51 -06:00
Ross Thompson
68745d40f2 Modified FPGA to add additional signals to ILA. Created advanced trigger for ILA using vivado's tsm language. 2021-12-12 17:21:44 -06:00
Ross Thompson
545c586186 Added proper credit to Richard Davis, the author of the original sd card reader. 2021-12-12 15:05:50 -06:00
kwan
a95efea0b3 Priviledged .* removed 2021-12-12 09:55:45 -08:00
kwan
82bab8e90e Privilige .*s removed 2021-12-12 09:54:14 -08:00
David Harris
a7e9dee77d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-12 05:49:31 -08:00
Kevin
1a82b50483 edited one testbench, yet to run regression 2021-12-10 20:26:20 -08:00
Ross Thompson
4cea8d1a29 Performance counters now output of coremark. 2021-12-09 14:48:17 -06:00
Ross Thompson
37079626cd Fixed numerous errors in the preformance counter updates. 
Fixed dcache reporting of access and misses.
Added performance counter tracking to coremark.
 2021-12-09 11:44:12 -06:00
bbracker
f7b2d3b6df fix recursive signal logging for graphical sims 2021-12-08 16:07:26 -08:00
bbracker
d6ae6824ab Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-08 14:12:18 -08:00
bbracker
f8cffca2b2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-08 14:12:09 -08:00
bbracker
5feccaec68 fix release of ReadDataM 2021-12-08 14:11:43 -08:00
slmnemo
e39f94b645 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 
help
 2021-12-08 14:09:58 -08:00
slmnemo
f2f15c0495 Removed .* from /wally-pipelined/src/uncore/uart.sv 2021-12-08 14:02:53 -08:00
Ross Thompson
f1ea52cb2d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-08 15:50:43 -06:00
Ross Thompson
741a21d0df Fixed some issues with the SDC having a different counter. When this is copied into synthesis the file names where the same and it gave a conflict. 
Remove preload from dtim.
 2021-12-08 15:50:15 -06:00
David Harris
bb49ba94a0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-08 13:48:49 -08:00
David Harris
a1f8f7babe Refactored IEU/ALU logic 2021-12-08 13:48:04 -08:00
Noah Limpert
5f0521d497 updated fcmp.sv instantiation to remove x*'s 2021-12-08 13:34:33 -08:00
David Harris
e14eb9872e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-08 12:33:59 -08:00
David Harris
d936342c97 Refactoring ALU and datapath muxes 2021-12-08 12:33:53 -08:00
Ross Thompson
8b7cefab79 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-08 13:40:44 -06:00
Ross Thompson
9ddd065340 Updated coremark testbench with the extra ports from FPGA merge. 
Fixed coremark Makefile to create work directory.
 2021-12-08 13:40:32 -06:00
bbracker
255cc26126 increase regression's expectations of buildroot to 246 million 2021-12-08 07:01:22 -08:00
slmnemo
7d614869a1 Removed .*s from wally-pipelined/src/uncore/uncore.sv 2021-12-08 01:03:02 -08:00
slmnemo
f413ea1b4a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-08 00:26:13 -08:00
Noah Limpert
15bdf5680e removed .* instantiation from ieu.sv and datapth.sv in ieu folder 2021-12-08 00:24:27 -08:00
slmnemo
021faaf8cd Removed .* from mmu instance inside lsu.sv. 2021-12-08 00:15:30 -08:00
Katherine Parry
80f026a734 FMA uses one LOA 2021-12-07 14:15:43 -08:00
bbracker
5a611bd82d undo intentionally breaking commit 2021-12-07 13:43:47 -08:00
bbracker
5d90f899b8 intentionally breaking commit 2021-12-07 13:27:34 -08:00
bbracker
c9808988c1 undo intentionally breaking commit 2021-12-07 13:27:06 -08:00
bbracker
2b41e37160 intentionally breaking commit 2021-12-07 13:23:19 -08:00
bbracker
8f73c1df9e 2nd attempt at making regression-wally.py able to be run from a different dir 2021-12-07 13:13:30 -08:00
bbracker
979580b1e7 fix checkpointing so that it can find the synchronized reset signal 2021-12-07 13:12:06 -08:00
bbracker
302bc56646 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-07 11:16:51 -08:00
bbracker
010339fa05 attempt to make regression-wally.py more path-independent such that git bisect can invoke it directly 2021-12-07 11:16:43 -08:00
Ross Thompson
4dbd5d45ee Added information on how to copy the linux image to flash card. 2021-12-07 13:16:38 -06:00
bbracker
2229e66d6c add buildroot tv linking to make-tests.sh 2021-12-07 11:15:59 -08:00
Ross Thompson
6c6b7865fb Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-07 13:12:59 -06:00
Ross Thompson
22721dd923 Added generate around the dtim preload. 
Added readme to explain FPGA.
 2021-12-07 13:12:47 -06:00
Ross Thompson
29743c5e9e Fixed two issues. 
First the xci files already include the xdc constraints for each IP block. There is no need to include the xdc files explicitly.
Second the bidir buffer for the sd card was connected backwards.
 2021-12-07 12:15:50 -06:00
bbracker
5a73ecd0be regression.py bugfix 2021-12-06 19:32:38 -08:00
bbracker
4df9093a7f add make-tests scripts 2021-12-06 15:37:33 -08:00
bbracker
7c44ecb364 add buildroot-only option to regression 2021-12-06 14:13:58 -08:00
bbracker
524bb0aa9a linux-testvectors symlinks shouldn't be in repo, especially not in this location 2021-12-05 22:03:51 -08:00
Ross Thompson
c3c9c327b7 Fixed more constraint issues in fpga. 
Added back in the ILA.
Design does not work yet.  Stil having issues with order of automatic
clock and I/O constraint ordering.
Added back in the preload for the boottim.
 2021-12-05 15:14:18 -06:00
David Harris
f45fe48158 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-04 20:26:01 -08:00
David Harris
64f33161bc Added files to repo 2021-12-04 20:25:33 -08:00
Skylar Litz
546f7fb4c2 fix some interrupt timing bugs 2021-12-03 12:32:38 -08:00
Ross Thompson
500e6ff430 Fixed buildroot to work with the fpga's merge. 2021-12-02 18:09:43 -06:00
Ross Thompson
b03ca464f1 Mostly integrated FPGA flow into main branch. Not all tests passing yet. 2021-12-02 18:00:32 -06:00
Ross Thompson
9ccc8e7f3a Merge branch 'fpga' into main 2021-12-02 14:28:10 -06:00
kwan
5164129172 .* resolved in ifu.sv 2021-12-02 10:32:35 -08:00
kwan
05a838aee2 .* in ifu/ifu.sv eliminated 2021-12-02 09:45:55 -08:00
David Harris
42780ba40b Added coremark scripts to regression directory 2021-12-01 09:08:06 -08:00
David Harris
a146d7a618 testing push 2021-11-30 11:20:09 -08:00
Ross Thompson
97c73f10ff Fixed uart for FPGA config after merge. This still needs some work. 2021-11-29 16:07:54 -06:00
Ross Thompson
a871118116 Merge branch 'main' into fpga 2021-11-29 10:10:37 -06:00
Ross Thompson
5642918ead Merge branch 'main' into fpga 2021-11-29 10:06:53 -06:00
bbracker
fed0bb08d6 UART hack now looks at physical addresses so that it isn't bamboozled by S-mode accesses 2021-11-25 11:01:59 -08:00
Noah Limpert
09d3322a26 updated fpu instantion on wallypiplinedhart to remove .*, updated spacing as well 2021-11-24 23:22:04 -08:00
Noah Limpert
93b626ce2a replaced .* instation of priv module on wallypiplinedhart 2021-11-24 22:58:59 -08:00
Noah Limpert
f36cc7a2a3 Made abhlite instation on wallypipehart more clear, updated spacing for consistency 2021-11-24 22:48:01 -08:00
Noah Limpert
5b7c969170 updated module instation of LSU on wallypiplinedhard 2021-11-24 22:09:39 -08:00
bbracker
23194c0308 fix parseState.py to correctly take in PMPCFG 2021-11-24 16:52:51 -08:00
Ross Thompson
1183aed049 Missed another change to uart. 2021-11-23 10:20:47 -06:00
Ross Thompson
3fc370654d Fixed syntax error which modelsim did not detect in my changes for making uart work with qemu's simulation. 2021-11-23 10:00:32 -06:00
Ross Thompson
f12e7e1b68 Added QEMU hack for initial LCR value in uart. 2021-11-22 15:23:19 -06:00
Ross Thompson
f05a66acd1 Hack added to uart so QEMU simulation can work with an ultra fast baud rate relative to the clock speed. 2021-11-22 15:20:54 -06:00
Ross Thompson
d5cf6da6eb Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-11-22 11:30:14 -06:00
bbracker
cffb72042a activate STVAL for buildroot 2021-11-21 10:40:28 -08:00
Ross Thompson
e955b17500 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-11-20 22:44:45 -06:00
Ross Thompson
055a5bd202 Removed unneeded check for icache ways. 2021-11-20 22:44:37 -06:00
Ross Thompson
9d3261ed49 Reversed bit order in uart. 2021-11-20 22:43:05 -06:00
Ross Thompson
88b4e0946f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-11-20 22:37:15 -06:00
Ross Thompson
705572f0ac Fixed a very complex interaction between interrupts, the icache, dcache, and hptw. 
If an interrupt occurred at the start of an ITLB miss or DTLB miss the page table
walk should be aborted before starting.
 2021-11-20 22:35:47 -06:00
bbracker
4e96d0f1db add checkpoints to regression 2021-11-20 19:42:53 -08:00
bbracker
e5d3416258 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-19 20:25:06 -08:00
bbracker
713aa7faac automatic bug finder script 2021-11-19 20:25:00 -08:00
bbracker
c07caf4fe8 increase buildroot progress expecttions; increase timeout to 20 hours 2021-11-19 12:52:11 -08:00
David Harris
82cfebfb83 Coremark Cleanup, trying compile from addins 2021-11-19 06:09:04 -08:00
David Harris
a801e0dbec Moved exe2memfile.pl 2021-11-18 20:32:13 -08:00
David Harris
690410721d Cleaning up CoreMark benchmark 2021-11-18 20:12:52 -08:00
David Harris
8e8b84f532 vert "Simplifying riscv-coremark" 
This reverts commit ce8232e396.
 2021-11-18 18:40:13 -08:00
David Harris
ce8232e396 Simplifying riscv-coremark 2021-11-18 17:15:40 -08:00
David Harris
b73e6354e3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-18 16:14:42 -08:00
David Harris
402b473dbb CoreMark testing 2021-11-18 16:14:25 -08:00
slmnemo
0bf1836a3a Removed .* from hazard hzu(.*). 2021-11-17 14:21:23 -08:00
slmnemo
5c28553ca1 Removed .* from hazard hzu(.*) in wallypipelinedhart.sv. 2021-11-17 14:08:08 -08:00
slmnemo
df6c54a664 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-17 13:38:51 -08:00
slmnemo
bf8cef78bc removed .* from muldiv.sv (REAL) 2021-11-17 13:37:50 -08:00
David Harris
0a281a06e0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-17 13:28:33 -08:00
Noah Limpert
b63c0f35d1 ieu variable naming changed for clarity 2021-11-17 13:24:28 -08:00
slmnemo
c5c886ddc1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-17 13:23:20 -08:00
slmnemo
40efffc70b Removed .*s from muldiv.sv 2021-11-17 13:23:12 -08:00
Noah Limpert
bbd17e730b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-17 13:04:33 -08:00
Noah Limpert
70a84b56c8 Updated IFU variable naming for clarity 2021-11-17 12:39:05 -08:00
Kevin Kim
6437c04074 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-17 12:18:25 -08:00
Kevin Kim
38437c664e root level makefile added 2021-11-17 12:17:56 -08:00
Kip Macsai-Goren
7a8c21e71f renamed presrc to forwardedSrc, replaced SrcAE and SrcBE with Forwarded src in the muldiv 2021-11-17 10:53:17 -08:00
Ross Thompson
f4c221f20a Created separate memory interface for the ddr4 fpga memory from the soc internal memory dtim. 2021-11-17 12:47:19 -06:00
Ross Thompson
23e78c4842 Fixed uart by reversing the bit order on transmit. 
Set prescale to 0.
 2021-11-17 10:32:41 -06:00
Skylar Litz
6fde97b16c fixed interrupt timing bug 2021-11-16 16:46:17 -08:00
David Harris
c610be25a7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-16 12:30:55 -08:00
bbracker
2203590f9f get current privilege level from GDB for checkpoints 2021-11-15 14:49:00 -08:00
Ross Thompson
1c9670d739 Have linux booting. Not sure about uart, but uart is now part of the ILA and I can see TX changing. 2021-11-12 17:37:07 -06:00
Ross Thompson
7497422667 Changed several things. 
Removed the need to use async flip flops in SDC.
Added arrs, a synchronizer for reset.
I think this works with the real FPGA hardware.
The last build did not include this arrs but it worked.
 2021-11-12 11:13:50 -06:00
Skylar Litz
3dd83b3113 fix timing of delayed interrupt 2021-11-11 09:35:51 -08:00
David Harris
570f24a9e4 bringing Coremark back to life 2021-11-10 12:43:31 -08:00
Kevin Kim
7cb8b76ef6 Makefile added in regression directory: 
-cd's into imperas then runs make commands, finally running the tvLinker script
 2021-11-09 10:55:48 -08:00
bbracker
f6a555009b increase expectations for buildroot and timeout count 2021-11-06 14:57:29 -07:00