Added proper credit to Richard Davis, the author of the original sd card reader.

wally-pipelined/src/hazard/hazard.sv

@@ -27,16 +27,16 @@
 
 module hazard(
   // Detect hazards
-	      input logic  BPPredWrongE, CSRWritePendingDEM, RetM, TrapM,
-	      input logic  LoadStallD, StoreStallD, MulDivStallD, CSRRdStallD,
-	      input logic  LSUStall, ICacheStallF,
-              input logic  FPUStallD, FStallD,
-	      input logic  DivBusyE,FDivBusyE,
-	      input logic  EcallFaultM, BreakpointFaultM,
-        input logic  InvalidateICacheM,
+(* mark_debug = "true" *)	      input logic  BPPredWrongE, CSRWritePendingDEM, RetM, TrapM,
+(* mark_debug = "true" *)	      input logic  LoadStallD, StoreStallD, MulDivStallD, CSRRdStallD,
+(* mark_debug = "true" *)	      input logic  LSUStall, ICacheStallF,
+(* mark_debug = "true" *)              input logic  FPUStallD, FStallD,
+(* mark_debug = "true" *)	      input logic  DivBusyE,FDivBusyE,
+(* mark_debug = "true" *)	      input logic  EcallFaultM, BreakpointFaultM,
+(* mark_debug = "true" *)        input logic  InvalidateICacheM,
   // Stall & flush outputs
-	      output logic StallF, StallD, StallE, StallM, StallW,
-	      output logic FlushF, FlushD, FlushE, FlushM, FlushW
+(* mark_debug = "true" *)	      output logic StallF, StallD, StallE, StallM, StallW,
+(* mark_debug = "true" *)	      output logic FlushF, FlushD, FlushE, FlushM, FlushW
 );
 
   logic StallFCause, StallDCause, StallECause, StallMCause, StallWCause;

wally-pipelined/src/sdc/clkdivider.sv

@@ -1,8 +1,9 @@
 ///////////////////////////////////////////
 // clock divider.sv
 //
-// Written: Ross Thompson September 18, 2021
-// Modified: 
+// Written: Richard Davis
+// Modified: Ross Thompson September 18, 2021
+// Converted to system verilog.
 //
 // Purpose: clock divider for sd flash
 // 

wally-pipelined/src/sdc/counter.sv

@@ -1,8 +1,9 @@
 ///////////////////////////////////////////
 // counter.sv
 //
-// Written: Ross Thompson
-// Modified: 
+// Written: Richard Davis
+// Modified: Ross Thompson
+// Converted to system verilog.
 //
 // Purpose: basic up counter
 // 

wally-pipelined/src/sdc/crc16_sipo_np_ce.sv

@@ -1,8 +1,9 @@
 ///////////////////////////////////////////
 // crc16 sipo np ce
 //
-// Written: Ross Thompson September 18, 2021
-// Modified: 
+// Written: Richard Davis
+// Modified: Ross Thompson September 18, 2021
+// Converted to system verilog.
 //
 // Purpose: CRC16 generator SIPO using register_ce
 //              w/o appending any zero-bits to the message

wally-pipelined/src/sdc/crc7_pipo.sv

@@ -1,8 +1,9 @@
 ///////////////////////////////////////////
 // crc7 sipo np ce
 //
-// Written: Ross Thompson September 18, 2021
-// Modified: 
+// Written: Richard Davis
+// Modified: Ross Thompson September 18, 2021
+// Converted to system verilog.
 //
 // Purpose:  takes 40 bits of input, generates 7 bit CRC after a single
 // clock cycle!

wally-pipelined/src/sdc/crc7_sipo_np_ce.sv

@@ -1,8 +1,8 @@
 ///////////////////////////////////////////
 // crc16 sipo np ce
 //
-// Written: Ross Thompson September 18, 2021
-// Modified: 
+// Written: Richard Davis
+// Modified: Ross Thompson September 18, 2021
 //
 // Purpose: CRC7 generator SIPO using register_ce
 //          w/o appending any zero-bits othe message

wally-pipelined/src/sdc/piso_generic_ce.sv

@@ -1,8 +1,8 @@
 ///////////////////////////////////////////
 // piso generic ce
 //
-// Written: Ross Thompson September 18, 2021
-// Modified: 
+// Written: Richard Davis
+// Modified: Ross Thompson September 18, 2021
 //
 // 
 // A component of the Wally configurable RISC-V project.

wally-pipelined/src/sdc/sd_clk_fsm.sv

@@ -1,8 +1,8 @@
 ///////////////////////////////////////////
 // sd_clk_fsm.sv
 //
-// Written: Ross Thompson September 19, 2021
-// Modified: 
+// Written: Richard Davis
+// Modified: Ross Thompson September 19, 2021
 //
 // Purpose: Controls clock dividers.
 // Replaces s_disable_sd_clocks, s_select_hs_clk, s_enable_hs_clk

wally-pipelined/src/sdc/sd_cmd_fsm.sv

@@ -1,8 +1,8 @@
 ///////////////////////////////////////////
 // sd_clk_fsm.sv
 //
-// Written: Ross Thompson September 19, 2021
-// Modified: 
+// Written: Richard Davis
+// Modified: Ross Thompson September 19, 2021
 //
 // Purpose: Finite state machine for the SD CMD bus
 // 

wally-pipelined/src/sdc/sd_dat_fsm.sv

@@ -1,8 +1,8 @@
 ///////////////////////////////////////////
 // sd_dat_fsm.sv
 //
-// Written: Ross Thompson September 19, 2021
-// Modified: 
+// Written: Richard Davis
+// Modified: Ross Thompson September 19, 2021
 //
 // Purpose: Runs in parallel with sd_cmd_fsm to control activity on the DAT
 // bus of the SD card.

wally-pipelined/src/sdc/sd_top.sv

@@ -1,8 +1,8 @@
 ///////////////////////////////////////////
 // sd_top.sv
 //
-// Written: Ross Thompson September 19, 2021
-// Modified: 
+// Written: Richard Davis
+// Modified: Ross Thompson September 19, 2021
 //
 // Purpose: SD card controller
 // 

wally-pipelined/src/sdc/sipo_generic_ce.sv

@@ -1,8 +1,8 @@
 ///////////////////////////////////////////
 // sipo_generic_ce
 //
-// Written: Ross Thompson September 20, 2021
-// Modified: 
+// Written: Richard Davis
+// Modified: Ross Thompson September 20, 2021
 //
 // Purpose:  serial to n-bit parallel shift register using register_ce.
 // When given a n-bit word as input transmit the message serially MSB (leftmost)