Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Modified FPGA to add additional signals to ILA. Created advanced trigger for ILA using vivado's tsm language.

Browse Source
This commit is contained in:
Ross Thompson 2021-12-12 17:21:44 -06:00
parent f2628494e3
commit 68745d40f2
5 changed files with 58 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
fpga/constraints/debug2.xdc
View File

@ -389,7 +389,7 @@ connect_debug_port u_ila_0/probe87 [get_nets [list wallypipelinedsoc/hart/hzu/Br
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe88]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe88]
connect_debug_port u_ila_0/probe88 [get_nets [list wallypipelinedsoc/hart/hzu/InvalidateICacheMp ]]
connect_debug_port u_ila_0/probe88 [get_nets [list wallypipelinedsoc/hart/hzu/InvalidateICacheM ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe89]
@ -411,10 +411,11 @@ set_property port_width 1 [get_debug_ports u_ila_0/probe92]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe92]
connect_debug_port u_ila_0/probe92 [get_nets [list wallypipelinedsoc/hart/hzu/StallM ]]
# StallW is StallM. trying to connect to StallW causes issues.
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe93]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe93]
connect_debug_port u_ila_0/probe93 [get_nets [list wallypipelinedsoc/hart/hzu/StallW ]]
connect_debug_port u_ila_0/probe93 [get_nets [list wallypipelinedsoc/hart/hzu/StallM ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe94]
@ -445,3 +446,4 @@ create_debug_port u_ila_0 probe
set_property port_width 24 [get_debug_ports u_ila_0/probe99]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe99]
connect_debug_port u_ila_0/probe99 [get_nets [list {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[0]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[1]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[2]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[3]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[4]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[5]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[6]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[7]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[8]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[9]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[10]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[11]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[12]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[13]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[14]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[15]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[16]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[17]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[18]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[19]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[20]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[21]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[22]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[23]}]]

16
fpga/debug_notes.org Normal file
View File

@ -0,0 +1,16 @@
* December 12, 2021
Indefinite lockup in the dcache with STATE_PTW_FAULT_CPU_BUSY
InstrM = f884_3803
PCM = ffff_ffff_8030_8004
Indefinite lockup in the dcache with STATE_PTW_FAULT_CPU_BUSY
InstrM = 0207_ba03
PCM = ffff_ffff_8034_89fe
Indefinite lockup in the dcache with STATE_PTW_FAULT_CPU_BUSY
InstrM = 0016_c383
PCM = ffff_ffff_8030_7504
Indefinite lockup in the dcache with STATE_PTW_FAULT_CPU_BUSY
InstrM = 0006_a703
PCM = ffff_ffff_8028_fa02

2
fpga/generator/Makefile
View File

@ -3,7 +3,7 @@ dst := IP
all: FPGA
FPGA: IP
vivado -mode batch -source wally.tcl | tee wally.log
vivado -mode batch -source wally.tcl 2>&1 | tee wally.log
IP: $(dst)/xlnx_proc_sys_reset.log \
$(dst)/xlnx_ddr4.log \

36
fpga/trigger_issues.tsm Normal file
View File

@ -0,0 +1,36 @@
##################################################
#
# For info on creating trigger state machines:
# 1) In the main Vivado menu bar, select
# Window > Language Templates
# 2) In the Templates window, select
# Debug > Trigger State Machine
# 3) Refer to the entry 'Info' for an overview
# of the trigger state machine language.
#
# More information can be found in this document:
#
# Vivado Design Suite User Guide: Programming
# and Debugging (UG908)
#
##################################################
state state_reset:
if(wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState == 32'h00000015) then
reset_counter $counter0;
goto state_begin_count;
else
goto state_reset;
endif
state state_begin_count:
if($counter0 == 16'h0064) then
goto state_trigger;
elseif(wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState == 32'h00000015) then
increment_counter $counter0;
goto state_begin_count;
else
goto state_reset;
endif
state state_trigger:
trigger;

2
wally-pipelined/src/cache/icachefsm.sv vendored
View File

@ -114,7 +114,7 @@ module icachefsm
STATE_CPU_BUSY_SPILL
} statetype;
statetype CurrState, NextState;
(* mark_debug = "true" *) statetype CurrState, NextState;
logic PreCntEn;
// the FSM is always runing, do not stall.