forked from Github_Repos/cvw
Refactoring ALU and datapath muxes
This commit is contained in:
David Harris
parent
f45fe48158
commit
d936342c97
@ -1 +1 @@
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Subproject commit 84d043817f75f752c9873326475e11f16e3a6f7c
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Subproject commit be67c99bd461742aa1c100bcc0732657faae2230
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@ -1 +1 @@
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Subproject commit d22b280198e74b871e04fc0ddb622fb825fdae49
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Subproject commit ddcfa6cc3d80818140a459e590296c3079c5a3ec
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@ -1,2 +1,2 @@
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vsim -do "do wally-pipelined.do rv32g arch32f"
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vsim -do "do wally-pipelined.do rv32g arch32i"
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@ -10,7 +10,7 @@ module fcvt (
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input logic XInfE, // is X infinity
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input logic XDenormE, // is X denormalized
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input logic [10:0] BiasE, // bias - depends on precision (max exponent/2)
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input logic [`XLEN-1:0] SrcAE, // integer input
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input logic [`XLEN-1:0] ForwardedSrcAE, // integer input
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input logic [2:0] FOpCtrlE, // chooses which instruction is done (full list below)
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input logic [2:0] FrmE, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
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input logic FmtE, // precision 1 = double 0 = single
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@ -73,7 +73,7 @@ module fcvt (
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////////////////////////////////////////////////////////
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// position the input in the most significant bits
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assign IntIn = FOpCtrlE[2] ? {SrcAE, {64-`XLEN{1'b0}}} : {SrcAE[31:0], 32'b0};
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assign IntIn = FOpCtrlE[2] ? {ForwardedSrcAE, {64-`XLEN{1'b0}}} : {ForwardedSrcAE[31:0], 32'b0};
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// make the integer positive
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assign PosInt = IntIn[64-1]&~FOpCtrlE[1] ? -IntIn : IntIn;
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// determine the integer's sign
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@ -30,7 +30,7 @@ module fpu (
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input logic [2:0] FRM_REGW, // Rounding mode from CSR
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input logic [31:0] InstrD, // instruction from IFU
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input logic [`XLEN-1:0] ReadDataW,// Read data from memory
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input logic [`XLEN-1:0] SrcAE, // Integer input being processed (from IEU)
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input logic [`XLEN-1:0] ForwardedSrcAE, // Integer input being processed (from IEU)
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input logic StallE, StallM, StallW, // stall signals from HZU
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input logic FlushE, FlushM, FlushW, // flush signals from HZU
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input logic [4:0] RdM, RdW, // which FP register to write to (from IEU)
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@ -229,7 +229,7 @@ module fpu (
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.XSNaNE, .ClassResE);
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// Convert
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fcvt fcvt (.XSgnE, .XExpE, .XManE, .XZeroE, .XNaNE, .XInfE, .XDenormE, .BiasE, .SrcAE, .FOpCtrlE, .FmtE, .FrmE,
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fcvt fcvt (.XSgnE, .XExpE, .XManE, .XZeroE, .XNaNE, .XInfE, .XDenormE, .BiasE, .ForwardedSrcAE, .FOpCtrlE, .FmtE, .FrmE,
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.CvtResE, .CvtFlgE);
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// data to be stored in memory - to IEU
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@ -238,7 +238,7 @@ module fpu (
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assign FWriteDataE = FSrcYE[`XLEN-1:0];
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// Align SrcA to MSB when single precicion
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mux2 #(64) SrcAMux({{32{1'b1}}, SrcAE[31:0]}, {{64-`XLEN{1'b1}}, SrcAE}, FmtE, AlignedSrcAE);
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mux2 #(64) SrcAMux({{32{1'b1}}, ForwardedSrcAE[31:0]}, {{64-`XLEN{1'b1}}, ForwardedSrcAE}, FmtE, AlignedSrcAE);
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// select a result that may be written to the FP register
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mux5 #(64) FResMux(AlignedSrcAE, SgnResE, CmpResE, CvtResE, CvtFpResE, FResSelE, FResE);
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@ -27,62 +27,66 @@
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module alu #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] a, b,
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input logic [4:0] alucontrol,
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input logic [2:0] ALUControl,
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input logic [2:0] Funct3,
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output logic [WIDTH-1:0] result,
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output logic [2:0] flags);
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output logic [WIDTH-1:0] sum);
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logic [WIDTH-1:0] condinvb, presum, sum, shift, slt, sltu, bor;
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logic right, arith, w64;
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logic carry, zero, neg;
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logic [WIDTH-1:0] condinvb, sumtrunc, shift, slt, sltu, bor;
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logic right; //, arith, w64;
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logic carry, neg;
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logic lt, ltu;
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logic overflow;
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logic W64, SubArith, ALUOp;
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assign {W64, SubArith, ALUOp} = ALUControl;
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// addition
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assign condinvb = alucontrol[3] ? ~b : b;
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assign {carry, presum} = a + condinvb + {{(WIDTH-1){1'b0}},alucontrol[3]};
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// *** make sure condinvb is only applied when it should be (sub, slt/sltu)
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assign condinvb = SubArith ? ~b : b;
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assign {carry, sum} = a + condinvb + {{(WIDTH-1){1'b0}}, SubArith};
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// support W-type RV64I ADDW/SUBW/ADDIW that sign-extend 32-bit result to 64 bits
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generate
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if (WIDTH==64)
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assign sum = w64 ? {{32{presum[31]}}, presum[31:0]} : presum;
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assign sumtrunc = W64 ? {{32{sum[31]}}, sum[31:0]} : sum;
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else
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assign sum = presum;
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assign sumtrunc = sum;
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endgenerate
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// shifts
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assign arith = alucontrol[3]; // sra
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assign w64 = alucontrol[4];
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assign right = (alucontrol[2:0] == 3'b101); // sra or srl
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shifter sh(a, b[5:0], right, arith, w64, shift);
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// assign arith = alucontrol[3]; // sra
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// assign w64 = alucontrol[4];
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assign right = (Funct3[2:0] == 3'b101); // sra or srl
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shifter sh(a, b[5:0], right, SubArith, W64, shift);
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// OR optionally passes zero when ALUControl[3] is set, supporting lui
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assign bor = alucontrol[3] ? b : a|b;
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// *** not needed anymore; simplify control
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//assign bor = alucontrol[3] ? b : a|b;
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// condition code flags based on add/subtract output
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assign zero = (sum == 0);
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assign neg = sum[WIDTH-1];
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// overflow occurs when the numbers being added have the same sign
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// and the result has the opposite sign
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assign overflow = (a[WIDTH-1] ~^ condinvb[WIDTH-1]) & (a[WIDTH-1] ^ sum[WIDTH-1]);
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assign lt = neg ^ overflow;
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assign ltu = ~carry;
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assign flags = {zero, lt, ltu};
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// slt
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assign slt = {{(WIDTH-1){1'b0}}, lt};
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assign sltu = {{(WIDTH-1){1'b0}}, ltu};
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always_comb
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case (alucontrol[2:0])
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3'b000: result = sum; // add or sub
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3'b001: result = shift; // sll
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3'b010: result = slt; // slt
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3'b011: result = sltu; // sltu
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3'b100: result = a ^ b; // xor
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3'b101: result = shift; // sra or srl
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3'b110: result = bor; // or / pass through input b for lui
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3'b111: result = a & b; // and
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endcase
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if (~ALUOp) result = sumtrunc;
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else
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case (Funct3)
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3'b000: result = sumtrunc; // add or sub
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3'b001: result = shift; // sll
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3'b010: result = slt; // slt
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3'b011: result = sltu; // sltu
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3'b100: result = a ^ b; // xor
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3'b101: result = shift; // sra or srl
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3'b110: result = a | b; // or
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3'b111: result = a & b; // and
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endcase
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endmodule
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52
wally-pipelined/src/ieu/comparator.sv
Normal file
52
wally-pipelined/src/ieu/comparator.sv
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@ -0,0 +1,52 @@
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///////////////////////////////////////////
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// comparator.sv
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//
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// Written: David_Harris@hmc.edu 8 December 2021
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// Modified:
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//
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// Purpose: Branch comparison
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module comparator #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] a, b,
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output logic [2:0] flags);
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logic [WIDTH-1:0] bbar, diff;
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logic carry, zero, neg, overflow, lt, ltu;
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// NOTE: This can be replaced by some faster logic optimized
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// to just compute flags and not the difference.
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// subtraction
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assign bbar = ~b;
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assign {carry, diff} = a + bbar;
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// condition code flags based on add/subtract output
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assign zero = (diff == 0);
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assign neg = diff[WIDTH-1];
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// overflow occurs when the numbers being subtracted have the opposite sign
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// and the result has the opposite sign fron the first
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assign overflow = (a[WIDTH-1] ^ b[WIDTH-1]) & (a[WIDTH-1] ^ diff[WIDTH-1]);
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assign lt = neg ^ overflow;
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assign ltu = ~carry;
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assign flags = {zero, lt, ltu};
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endmodule
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@ -38,9 +38,9 @@ module controller(
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input logic StallE, FlushE,
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input logic [2:0] FlagsE,
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output logic PCSrcE, // for datapath and Hazard Unit
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output logic [4:0] ALUControlE,
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output logic [2:0] ALUControlE,
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output logic ALUSrcAE, ALUSrcBE,
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output logic TargetSrcE,
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output logic ALUResultSrcE,
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output logic MemReadE, CSRReadE, // for Hazard Unit
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output logic [2:0] Funct3E,
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output logic MulDivE, W64E,
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@ -70,7 +70,7 @@ module controller(
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logic [6:0] Funct7D;
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logic [4:0] Rs1D;
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`define CTRLW 24
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`define CTRLW 23
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// pipelined control signals
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logic RegWriteD, RegWriteE;
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@ -78,10 +78,10 @@ module controller(
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logic [1:0] MemRWD, MemRWE;
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logic JumpD;
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logic BranchD, BranchE;
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logic [1:0] ALUOpD;
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logic [4:0] ALUControlD;
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logic ALUOpD;
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logic [2:0] ALUControlD;
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logic ALUSrcAD, ALUSrcBD;
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logic TargetSrcD, W64D, MulDivD;
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logic ALUResultSrcD, W64D, MulDivD;
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logic CSRZeroSrcD;
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logic CSRReadD;
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logic [1:0] AtomicD;
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@ -92,12 +92,13 @@ module controller(
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logic PrivilegedD, PrivilegedE;
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logic InvalidateICacheE, FlushDCacheE;
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logic [`CTRLW-1:0] ControlsD;
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logic aluc3D;
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logic SubArithD;
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logic subD, sraD, sltD, sltuD;
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logic BranchTakenE;
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logic zeroE, ltE, ltuE;
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logic unused;
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logic BranchFlagE;
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// Extract fields
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assign OpD = InstrD[6:0];
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assign Funct3D = InstrD[14:12];
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@ -108,50 +109,50 @@ module controller(
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generate
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always_comb
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case(OpD)
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// RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_ALUOp_Jump_TargetSrc_W64_CSRRead_Privileged_Fence_MulDiv_Atomic_Illegal
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7'b0000000: ControlsD = `CTRLW'b0_000_00_00_000_0_00_0_0_0_0_0_0_0_00_1; // illegal instruction
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7'b0000011: ControlsD = `CTRLW'b1_000_01_10_001_0_00_0_0_0_0_0_0_0_00_0; // lw
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7'b0000111: ControlsD = `CTRLW'b0_000_01_10_001_0_00_0_0_0_0_0_0_0_00_0; // flw
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7'b0001111: ControlsD = `CTRLW'b0_000_00_00_000_0_00_0_0_0_0_0_1_0_00_0; // fence
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7'b0010011: ControlsD = `CTRLW'b1_000_01_00_000_0_10_0_0_0_0_0_0_0_00_0; // I-type ALU
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7'b0010111: ControlsD = `CTRLW'b1_100_11_00_000_0_00_0_0_0_0_0_0_0_00_0; // auipc
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// RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_ALUOp_Jump_ALUResultSrc_W64_CSRRead_Privileged_Fence_MulDiv_Atomic_Illegal
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7'b0000000: ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // illegal instruction
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7'b0000011: ControlsD = `CTRLW'b1_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0; // lw
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7'b0000111: ControlsD = `CTRLW'b0_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0; // flw
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7'b0001111: ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_1_0_00_0; // fence
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7'b0010011: ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_0_0_0_0_0_00_0; // I-type ALU
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7'b0010111: ControlsD = `CTRLW'b1_100_11_00_000_0_0_0_0_0_0_0_0_0_00_0; // auipc
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7'b0011011: if (`XLEN == 64)
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ControlsD = `CTRLW'b1_000_01_00_000_0_10_0_0_1_0_0_0_0_00_0; // IW-type ALU for RV64i
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ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_1_0_0_0_0_00_0; // IW-type ALU for RV64i
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else
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ControlsD = `CTRLW'b0_000_00_00_000_0_00_0_0_0_0_0_0_0_00_1; // non-implemented instruction
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7'b0100011: ControlsD = `CTRLW'b0_001_01_01_000_0_00_0_0_0_0_0_0_0_00_0; // sw
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7'b0100111: ControlsD = `CTRLW'b0_001_01_01_000_0_00_0_0_0_0_0_0_0_00_0; // fsw
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ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // non-implemented instruction
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7'b0100011: ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0; // sw
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7'b0100111: ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0; // fsw
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7'b0101111: if (`A_SUPPORTED) begin
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if (InstrD[31:27] == 5'b00010)
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ControlsD = `CTRLW'b1_000_00_10_001_0_00_0_0_0_0_0_0_0_01_0; // lr
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ControlsD = `CTRLW'b1_000_00_10_001_0_0_0_0_0_0_0_0_0_01_0; // lr
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else if (InstrD[31:27] == 5'b00011)
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ControlsD = `CTRLW'b1_101_01_01_100_0_00_0_0_0_0_0_0_0_01_0; // sc
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ControlsD = `CTRLW'b1_101_01_01_100_0_0_0_0_0_0_0_0_0_01_0; // sc
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else
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ControlsD = `CTRLW'b1_101_01_11_001_0_00_0_0_0_0_0_0_0_10_0;; // amo
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ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0;; // amo
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end else
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ControlsD = `CTRLW'b0_000_00_00_000_0_00_0_0_0_0_0_0_0_00_1; // non-implemented instruction
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ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // non-implemented instruction
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7'b0110011: if (Funct7D == 7'b0000000 || Funct7D == 7'b0100000)
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ControlsD = `CTRLW'b1_000_00_00_000_0_10_0_0_0_0_0_0_0_00_0; // R-type
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ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0; // R-type
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else if (Funct7D == 7'b0000001 && `M_SUPPORTED)
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ControlsD = `CTRLW'b1_000_00_00_011_0_00_0_0_0_0_0_0_1_00_0; // Multiply/Divide
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ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0; // Multiply/Divide
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else
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ControlsD = `CTRLW'b0_000_00_00_000_0_00_0_0_0_0_0_0_0_00_1; // non-implemented instruction
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7'b0110111: ControlsD = `CTRLW'b1_100_01_00_000_0_11_0_0_0_0_0_0_0_00_0; // lui
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ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // non-implemented instruction
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7'b0110111: ControlsD = `CTRLW'b1_100_01_00_000_0_0_0_1_0_0_0_0_0_00_0; // lui
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7'b0111011: if ((Funct7D == 7'b0000000 || Funct7D == 7'b0100000) && `XLEN == 64)
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ControlsD = `CTRLW'b1_000_00_00_000_0_10_0_0_1_0_0_0_0_00_0; // R-type W instructions for RV64i
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ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_1_0_0_0_0_00_0; // R-type W instructions for RV64i
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else if (Funct7D == 7'b0000001 && `M_SUPPORTED && `XLEN == 64)
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ControlsD = `CTRLW'b1_000_00_00_011_0_00_0_0_1_0_0_0_1_00_0; // W-type Multiply/Divide
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||||
ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_1_0_0_0_1_00_0; // W-type Multiply/Divide
|
||||
else
|
||||
ControlsD = `CTRLW'b0_000_00_00_000_0_00_0_0_0_0_0_0_0_00_1; // non-implemented instruction
|
||||
ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // non-implemented instruction
|
||||
//7'b1010011: ControlsD = `CTRLW'b0_000_00_00_101_0_00_0_0_0_0_0_0_0_00_1; // FP
|
||||
7'b1100011: ControlsD = `CTRLW'b0_010_00_00_000_1_01_0_0_0_0_0_0_0_00_0; // beq
|
||||
7'b1100111: ControlsD = `CTRLW'b1_000_00_00_000_0_00_1_1_0_0_0_0_0_00_0; // jalr
|
||||
7'b1101111: ControlsD = `CTRLW'b1_011_00_00_000_0_00_1_0_0_0_0_0_0_00_0; // jal
|
||||
7'b1100011: ControlsD = `CTRLW'b0_010_00_00_000_1_0_0_0_0_0_0_0_0_00_0; // beq
|
||||
7'b1100111: ControlsD = `CTRLW'b1_000_00_00_000_0_0_1_1_0_0_0_0_0_00_0; // jalr
|
||||
7'b1101111: ControlsD = `CTRLW'b1_011_00_00_000_0_0_1_1_0_0_0_0_0_00_0; // jal
|
||||
7'b1110011: if (Funct3D == 3'b000)
|
||||
ControlsD = `CTRLW'b0_000_00_00_000_0_00_0_0_0_0_1_0_0_00_0; // privileged; decoded further in priveleged modules
|
||||
ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_1_0_0_00_0; // privileged; decoded further in priveleged modules
|
||||
else
|
||||
ControlsD = `CTRLW'b1_000_00_00_010_0_00_0_0_0_1_0_0_0_00_0; // csrs
|
||||
default: ControlsD = `CTRLW'b0_000_00_00_000_0_00_0_0_0_0_0_0_0_00_1; // non-implemented instruction
|
||||
ControlsD = `CTRLW'b1_000_00_00_010_0_0_0_0_0_1_0_0_0_00_0; // csrs
|
||||
default: ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // non-implemented instruction
|
||||
endcase
|
||||
endgenerate
|
||||
|
||||
@ -159,7 +160,7 @@ module controller(
|
||||
// squash control signals if coming from an illegal compressed instruction
|
||||
assign IllegalBaseInstrFaultD = ControlsD[0];
|
||||
assign {RegWriteD, ImmSrcD, ALUSrcAD, ALUSrcBD, MemRWD,
|
||||
ResultSrcD, BranchD, ALUOpD, JumpD, TargetSrcD, W64D, CSRReadD,
|
||||
ResultSrcD, BranchD, ALUOpD, JumpD, ALUResultSrcD, W64D, CSRReadD,
|
||||
PrivilegedD, FenceD, MulDivD, AtomicD, unused} = IllegalIEUInstrFaultD ? `CTRLW'b0 : ControlsD;
|
||||
// *** move Privileged, CSRwrite?? Or move controller out of IEU into datapath and handle all instructions
|
||||
|
||||
@ -172,15 +173,19 @@ module controller(
|
||||
assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]);
|
||||
assign sraD = (Funct3D == 3'b101 & Funct7D[5]);
|
||||
|
||||
assign aluc3D = subD | sraD | sltD | sltuD; // TRUE for R-type subtracts and sra, slt, sltu
|
||||
assign SubArithD = subD | sraD | sltD | sltuD; // TRUE for R-type subtracts and sra, slt, sltu
|
||||
// assign SubArithD = aluc3D; // ***cleanup
|
||||
|
||||
always_comb
|
||||
// *** replace all of this
|
||||
assign ALUControlD = {W64D, SubArithD, ALUOpD};
|
||||
/* always_comb
|
||||
case(ALUOpD)
|
||||
2'b00: ALUControlD = 5'b00000; // addition
|
||||
2'b01: ALUControlD = 5'b01000; // subtraction
|
||||
2'b11: ALUControlD = 5'b01110; // pass B through for lui
|
||||
2'b01: ALUControlD = 5'b00000; // add for branch offset
|
||||
// 2'b01: ALUControlD = 5'b01000; // subtraction
|
||||
// 2'b11: ALUControlD = 5'b01110; // pass B through for lui ***no longer used
|
||||
default: ALUControlD = {W64D, aluc3D, Funct3D}; // R-type instructions
|
||||
endcase
|
||||
endcase*/
|
||||
|
||||
// Fences
|
||||
// Ordinary fence is presently a nop
|
||||
@ -201,14 +206,15 @@ module controller(
|
||||
flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD);
|
||||
|
||||
// Execute stage pipeline control register and logic
|
||||
flopenrc #(29) controlregE(clk, reset, FlushE, ~StallE,
|
||||
{RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, TargetSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, MulDivD, AtomicD, InvalidateICacheD, FlushDCacheD, InstrValidD},
|
||||
{RegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, TargetSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, MulDivE, AtomicE, InvalidateICacheE, FlushDCacheE, InstrValidE});
|
||||
flopenrc #(27) controlregE(clk, reset, FlushE, ~StallE,
|
||||
{RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, MulDivD, AtomicD, InvalidateICacheD, FlushDCacheD, InstrValidD},
|
||||
{RegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, MulDivE, AtomicE, InvalidateICacheE, FlushDCacheE, InstrValidE});
|
||||
|
||||
// Branch Logic
|
||||
assign {zeroE, ltE, ltuE} = FlagsE;
|
||||
|
||||
always_comb
|
||||
mux4 #(1) branchflagmux(zeroE, 1'b0, ltE, ltuE, Funct3E[2:1], BranchFlagE);
|
||||
assign BranchTakenE = BranchFlagE ^ Funct3E[0];
|
||||
/* always_comb
|
||||
case(Funct3E)
|
||||
3'b000: BranchTakenE = zeroE; // beq
|
||||
3'b001: BranchTakenE = ~zeroE; // bne
|
||||
@ -217,7 +223,7 @@ module controller(
|
||||
3'b110: BranchTakenE = ltuE; // bltu
|
||||
3'b111: BranchTakenE = ~ltuE; // bgeu
|
||||
default: BranchTakenE = 1'b0; // undefined mode
|
||||
endcase
|
||||
endcase*/
|
||||
|
||||
assign PCSrcE = JumpE | BranchE & BranchTakenE;
|
||||
|
||||
|
||||
@ -30,12 +30,13 @@ module datapath (
|
||||
// Decode stage signals
|
||||
input logic [2:0] ImmSrcD,
|
||||
input logic [31:0] InstrD,
|
||||
input logic [2:0] Funct3E,
|
||||
// Execute stage signals
|
||||
input logic StallE, FlushE,
|
||||
input logic [1:0] ForwardAE, ForwardBE,
|
||||
input logic [4:0] ALUControlE,
|
||||
input logic [2:0] ALUControlE,
|
||||
input logic ALUSrcAE, ALUSrcBE,
|
||||
input logic TargetSrcE,
|
||||
input logic ALUResultSrcE,
|
||||
input logic JumpE,
|
||||
input logic IllegalFPUInstrE,
|
||||
input logic [`XLEN-1:0] FWriteDataE,
|
||||
@ -44,7 +45,6 @@ module datapath (
|
||||
output logic [2:0] FlagsE,
|
||||
output logic [`XLEN-1:0] PCTargetE,
|
||||
output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
|
||||
output logic [`XLEN-1:0] SrcAE, SrcBE,
|
||||
// Memory stage signals
|
||||
input logic StallM, FlushM,
|
||||
input logic FWriteIntM,
|
||||
@ -75,11 +75,12 @@ module datapath (
|
||||
logic [`XLEN-1:0] ExtImmE;
|
||||
|
||||
// logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, SrcAE2, SrcBE2; // *** MAde forwardedsrcae an output to get rid of a mux in the critical path.
|
||||
logic [`XLEN-1:0] SrcAE, SrcBE;
|
||||
logic [`XLEN-1:0] SrcAE2, SrcBE2;
|
||||
|
||||
logic [`XLEN-1:0] ALUResultE;
|
||||
logic [`XLEN-1:0] ALUResultE, AltResultE, ALUPreResultE;
|
||||
logic [`XLEN-1:0] WriteDataE;
|
||||
logic [`XLEN-1:0] TargetBaseE;
|
||||
logic [`XLEN-1:0] AddressE;
|
||||
// Memory stage signals
|
||||
logic [`XLEN-1:0] ALUResultM;
|
||||
logic [`XLEN-1:0] ResultM;
|
||||
@ -110,18 +111,23 @@ module datapath (
|
||||
mux3 #(`XLEN) fbemux(RD2E, WriteDataW, ResultM, ForwardBE, ForwardedSrcBE);
|
||||
mux2 #(`XLEN) writedatamux(ForwardedSrcBE, FWriteDataE, ~IllegalFPUInstrE, WriteDataE);
|
||||
mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE);
|
||||
mux2 #(`XLEN) srcamux2(SrcAE, PCLinkE, JumpE, SrcAE2);
|
||||
// mux2 #(`XLEN) srcamux2(SrcAE, PCLinkE, JumpE, SrcAE2);
|
||||
mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ExtImmE, ALUSrcBE, SrcBE);
|
||||
mux2 #(`XLEN) srcbmux2(SrcBE, {`XLEN{1'b0}}, JumpE, SrcBE2); // *** May be able to remove this mux.
|
||||
alu #(`XLEN) alu(SrcAE2, SrcBE2, ALUControlE, ALUResultE, FlagsE);
|
||||
mux2 #(`XLEN) targetsrcmux(PCE, SrcAE, TargetSrcE, TargetBaseE);
|
||||
assign PCTargetE = ExtImmE + TargetBaseE;
|
||||
// mux2 #(`XLEN) srcbmux2(SrcBE, {`XLEN{1'b0}}, JumpE, SrcBE2); // *** May be able to remove this mux.
|
||||
alu #(`XLEN) alu(SrcAE/*SrcAE2*/, SrcBE/*SrcBE2*/, ALUControlE, Funct3E, ALUPreResultE, AddressE /*, FlagsE */);
|
||||
// redo ALUControlE to simplify - jus needs ALUAddE, Funct3E, W64E
|
||||
comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, FlagsE);
|
||||
// mux2 #(`XLEN) targetsrcmux(PCE, SrcAE, TargetSrcE, TargetBaseE); // *** PCE alsready should be selectable for SrcAE
|
||||
// assign PCTargetE = ExtImmE + TargetBaseE;
|
||||
mux2 #(`XLEN) altresultmux(ExtImmE, PCLinkE, JumpE, AltResultE);
|
||||
mux2 #(`XLEN) aluresultmux(ALUPreResultE, AltResultE, ALUResultSrcE, ALUResultE);
|
||||
|
||||
// Memory stage pipeline register
|
||||
flopenrc #(`XLEN) SrcAMReg(clk, reset, FlushM, ~StallM, SrcAE, SrcAM);
|
||||
flopenrc #(`XLEN) ALUResultMReg(clk, reset, FlushM, ~StallM, ALUResultE, ALUResultM);
|
||||
assign MemAdrM = ALUResultM;
|
||||
assign MemAdrE = ALUResultE;
|
||||
assign MemAdrE = AddressE; // *** clean up this naming
|
||||
assign PCTargetE = AddressE; // *** clean up this naming
|
||||
flopenrc #(`XLEN) AddressNReg(clk, reset, FlushM, ~StallM, MemAdrE, MemAdrM);
|
||||
flopenrc #(`XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, WriteDataE, WriteDataM);
|
||||
flopenrc #(5) RdMEg(clk, reset, FlushM, ~StallM, RdE, RdM);
|
||||
mux2 #(`XLEN) resultmuxM(ALUResultM, FIntResM, FWriteIntM, ResultM);
|
||||
|
||||
@ -41,7 +41,7 @@ module ieu (
|
||||
output logic MulDivE, W64E,
|
||||
output logic [2:0] Funct3E,
|
||||
output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
|
||||
output logic [`XLEN-1:0] SrcAE, SrcBE,
|
||||
// output logic [`XLEN-1:0] SrcAE, SrcBE,
|
||||
input logic FWriteIntM,
|
||||
|
||||
// Memory stage interface
|
||||
@ -76,10 +76,10 @@ module ieu (
|
||||
|
||||
logic [2:0] ImmSrcD;
|
||||
logic [2:0] FlagsE;
|
||||
logic [4:0] ALUControlE;
|
||||
logic [2:0] ALUControlE;
|
||||
logic ALUSrcAE, ALUSrcBE;
|
||||
logic [2:0] ResultSrcW;
|
||||
logic TargetSrcE;
|
||||
logic ALUResultSrcE;
|
||||
logic SCE;
|
||||
logic [4:0] RdE;
|
||||
|
||||
|
||||
@ -60,7 +60,7 @@ module wallypipelinedhart (
|
||||
logic CSRReadM, CSRWriteM, PrivilegedM;
|
||||
logic [1:0] AtomicE;
|
||||
logic [1:0] AtomicM;
|
||||
logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, SrcAE, SrcBE;
|
||||
logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE; //, SrcAE, SrcBE;
|
||||
logic [`XLEN-1:0] SrcAM;
|
||||
logic [2:0] Funct3E;
|
||||
// logic [31:0] InstrF;
|
||||
@ -211,7 +211,8 @@ module wallypipelinedhart (
|
||||
.PCE, .PCLinkE, .FWriteIntE, .IllegalFPUInstrE,
|
||||
.FWriteDataE, .PCTargetE, .MulDivE, .W64E,
|
||||
.Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
|
||||
.SrcAE, .SrcBE, .FWriteIntM,
|
||||
//.SrcAE, .SrcBE,
|
||||
.FWriteIntM,
|
||||
|
||||
// Memory stage interface
|
||||
.SquashSCW, // from LSU
|
||||
@ -364,7 +365,7 @@ module wallypipelinedhart (
|
||||
.FRM_REGW, // Rounding mode from CSR
|
||||
.InstrD, // instruction from IFU
|
||||
.ReadDataW,// Read data from memory
|
||||
.SrcAE, // Integer input being processed (from IEU)
|
||||
.ForwardedSrcAE, // Integer input being processed (from IEU)
|
||||
.StallE, .StallM, .StallW, // stall signals from HZU
|
||||
.FlushE, .FlushM, .FlushW, // flush signals from HZU
|
||||
.RdM, .RdW, // which FP register to write to (from IEU)
|
||||
|
||||
@ -32,11 +32,12 @@
|
||||
`include "wally-config.vh"
|
||||
|
||||
module wallypipelinedsoc (
|
||||
input logic clk, reset_ext,
|
||||
input logic clk, reset_ext,
|
||||
output logic reset,
|
||||
// AHB Lite Interface
|
||||
// inputs from external memory
|
||||
input logic [`AHBW-1:0] HRDATAEXT,
|
||||
input logic HREADYEXT, HRESPEXT,
|
||||
input logic [`AHBW-1:0] HRDATAEXT,
|
||||
input logic HREADYEXT, HRESPEXT,
|
||||
output logic HSELEXT,
|
||||
// outputs to external memory, shared with uncore memory
|
||||
output logic HCLK, HRESETn,
|
||||
@ -62,7 +63,7 @@ module wallypipelinedsoc (
|
||||
);
|
||||
|
||||
// Uncore signals
|
||||
logic reset;
|
||||
// logic reset;
|
||||
logic [`AHBW-1:0] HRDATA; // from AHB mux in uncore
|
||||
logic HRESP;
|
||||
logic TimerIntM, SwIntM; // from CLINT
|
||||
|
||||
Loading…
Reference in New Issue
Block a user