Ross Thompson
840e814e95
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-25 19:21:04 -06:00
David Harris
8d04e83c9f
simpleram simplification
2022-01-25 19:46:13 +00:00
David Harris
9da1ed4ed9
simpleram simplification
2022-01-25 19:40:07 +00:00
David Harris
a86a9f5c2a
simpleram simplification
2022-01-25 18:26:31 +00:00
David Harris
e3136c9a1e
simpleram address simplification
2022-01-25 18:17:33 +00:00
David Harris
7ad2eb009a
simpleram address simplification
2022-01-25 18:00:50 +00:00
David Harris
6a555032eb
simpleram clk and reset simplification
2022-01-25 17:34:15 +00:00
David Harris
cf50beb958
Start of IFU cleanup
2022-01-25 17:31:53 +00:00
Ross Thompson
8ef70389d3
Added spill support back into the IROM IFU.
2022-01-21 15:50:54 -06:00
Ross Thompson
9982549057
Changed the IROM and DTIM memories to behave like edge-triggered srams.
2022-01-21 15:42:54 -06:00
Ross Thompson
e2343699d1
Factored out InstrValidNotFlushedM from each csr*.sv to csr.sv
2022-01-20 16:39:54 -06:00
David Harris
07425369fc
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
Ross Thompson
acec56c27e
Added PCNextF and PostSpillInstrRawF to ila.
2022-01-19 14:05:14 -06:00
Ross Thompson
4a75e69457
Merged in the debug ila updates.
2022-01-18 17:29:21 -06:00
Ross Thompson
28859f959b
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-18 17:19:59 -06:00
Ross Thompson
a5f773220e
Updated CSR modules to prevent writting the registers when flushing. This only effects architecture writes not side effect writes.
2022-01-18 17:19:33 -06:00
David Harris
55b4423329
Added E extension, and downloaded riscv-dv and embench-iot to addins
2022-01-17 14:42:59 +00:00
David Harris
bd320c2f76
lsu cleanup down to 346 lines
2022-01-15 01:19:44 +00:00
David Harris
325724f556
LSU Cleanup
2022-01-15 01:11:17 +00:00
David Harris
6febce0001
Moved Dcache into bus block
2022-01-15 00:39:07 +00:00
David Harris
fd13272d4c
Renamed LSUStall to LSUStallM
2022-01-15 00:24:16 +00:00
David Harris
db2271b7e0
LSU cleanup
2022-01-15 00:11:30 +00:00
David Harris
dab3c754d7
LSU cleanup
2022-01-15 00:03:03 +00:00
David Harris
2bf4676ff8
LSU cleanup
2022-01-14 23:55:27 +00:00
Ross Thompson
03010845f5
Fixed spillthreshold warning.
2022-01-14 17:23:39 -06:00
Ross Thompson
ba10e9dfe8
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-14 17:16:53 -06:00
David Harris
43abf25417
moved fp to tests
2022-01-14 23:05:59 +00:00
David Harris
218a8e6eaa
LSU partitioning
2022-01-14 23:02:28 +00:00
Ross Thompson
73ad5715f4
Cleanup IFU comments.
2022-01-14 15:06:30 -06:00
Ross Thompson
b8f4eb2997
Optimization in the ifu. Please note this optimization is not strictly correct,
...
but is possible. See comments in the ifu source code for details.
2022-01-14 12:16:48 -06:00
Ross Thompson
2e8f5e06bd
More ifu cleanup.
2022-01-14 11:19:12 -06:00
Ross Thompson
3bec276862
Added tim only test to regression-wally. Minor cleanup to ifu.
2022-01-14 11:13:06 -06:00
Ross Thompson
a973681a90
Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.
2022-01-13 22:21:43 -06:00
Ross Thompson
aad28366d7
Partial local dtim in lsu configuration.
2022-01-13 17:50:31 -06:00
Ross Thompson
e6e3b0607a
Merge branch 'testDivInterruptInterlock' into main
2022-01-13 11:21:48 -06:00
Ross Thompson
f870b8b3d3
Fixed interger divide so it can be interrupted.
2022-01-13 11:16:50 -06:00
Ross Thompson
66f3259984
Removed unused inputs to hptw.
2022-01-13 11:04:48 -06:00
Ross Thompson
a23e6efd5c
Fixed bug in the lsu's write back data. If an AMO was uncached it would not be corrected executed because the write data to the bus would not include the amoalu.
2022-01-12 17:41:39 -06:00
Ross Thompson
85b5dc08a8
Fixed support to allow spills and no icache.
2022-01-12 17:25:16 -06:00
Ross Thompson
e06fb923a1
Better solution to the integer divider interrupt interaction.
2022-01-12 14:22:18 -06:00
Ross Thompson
11f1613d59
Added additional fsm to ILA.
2022-01-12 14:17:16 -06:00
Ross Thompson
d8173745bb
Possible fix for the TrapM DTLBMiss suppression.
2022-01-12 14:17:16 -06:00
Ross Thompson
cd75bf98e1
If a trap occurs concurrent with a I/DTLB miss the interlock fsm incorrectly goes into the states to handle the TLB miss.
...
This commit fixes this bug by keeping the interlock fsm in the T0_READY state on TrapM.
2022-01-12 14:17:16 -06:00
Ross Thompson
b294f1fbb0
Oups. My hack for DivE interrupt prevention was wrong.
2022-01-12 14:17:16 -06:00
Ross Thompson
459f4bd3b4
Hack "fix" to prevent interrupt from occuring during an integer divide.
...
This is not the desired solution but will allow continued debuging of linux.
2022-01-12 14:17:16 -06:00
Ross Thompson
73c488914f
Added icache access and icache miss to performance counters.
2022-01-09 22:56:56 -06:00
Ross Thompson
509a0cd3f8
Fixed bug with interlock fsm. The interlock fsm should suppress bus and cache requests by the cpu
...
only at the start of a request. Pending interrupt was used to start one of these suppressions;
however because of the way the cache's fsm was separated from the bus fsm, the cache now made requests
to the bus fsm. On a miss with write back, the inital fetch is handled correctly. However if an
interrupt becam pending then the the next request (eviction) made by the cache was also suppressed.
This keeps the d cache fsm stuck in the STATE_MISS_EVICT_DIRTY state as it think it has made a request
to the bus fsm, but the pending interrupt ignored the request.
The solution is to modify how cpu requests are suppressed. Instead of relying on pending interrupt
it is better to use interrupt which will be disabled if the dcache is currently processing the evict.
2022-01-07 17:55:34 -06:00
David Harris
120fb7863f
Reformatted MIT license to 95 characters
2022-01-07 12:58:40 +00:00
David Harris
fedb9d3287
moved proposed-sdc
2022-01-07 12:44:21 +00:00
David Harris
40af3abef9
piplined directory cleanup
2022-01-07 12:43:50 +00:00
