forked from Github_Repos/cvw
moved fp to tests
This commit is contained in:
commit
43abf25417
@ -50,9 +50,9 @@
|
||||
`define UARCH_PIPELINED 1
|
||||
`define UARCH_SUPERSCALR 0
|
||||
`define UARCH_SINGLECYCLE 0
|
||||
`define MEM_DTIM 1
|
||||
`define MEM_DTIM 0
|
||||
`define MEM_DCACHE 1
|
||||
`define MEM_IROM 1
|
||||
`define MEM_IROM 0
|
||||
`define MEM_ICACHE 1
|
||||
`define MEM_VIRTMEM 1
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
|
@ -48,9 +48,9 @@
|
||||
`define UARCH_PIPELINED 1
|
||||
`define UARCH_SUPERSCALR 0
|
||||
`define UARCH_SINGLECYCLE 0
|
||||
`define MEM_DTIM 1
|
||||
`define MEM_DTIM 0
|
||||
`define MEM_DCACHE 1
|
||||
`define MEM_IROM 1
|
||||
`define MEM_IROM 0
|
||||
`define MEM_ICACHE 1
|
||||
`define MEM_VIRTMEM 1
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
|
@ -50,9 +50,9 @@
|
||||
`define UARCH_PIPELINED 1
|
||||
`define UARCH_SUPERSCALR 0
|
||||
`define UARCH_SINGLECYCLE 0
|
||||
`define MEM_DTIM 1
|
||||
`define MEM_DTIM 0
|
||||
`define MEM_DCACHE 1
|
||||
`define MEM_IROM 1
|
||||
`define MEM_IROM 0
|
||||
`define MEM_ICACHE 1
|
||||
`define MEM_VIRTMEM 1
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
|
@ -49,9 +49,9 @@
|
||||
`define UARCH_PIPELINED 1
|
||||
`define UARCH_SUPERSCALR 0
|
||||
`define UARCH_SINGLECYCLE 0
|
||||
`define MEM_DTIM 1
|
||||
`define MEM_DTIM 0
|
||||
`define MEM_DCACHE 1
|
||||
`define MEM_IROM 1
|
||||
`define MEM_IROM 0
|
||||
`define MEM_ICACHE 1
|
||||
`define MEM_VIRTMEM 1
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
|
@ -49,9 +49,9 @@
|
||||
`define UARCH_PIPELINED 1
|
||||
`define UARCH_SUPERSCALR 0
|
||||
`define UARCH_SINGLECYCLE 0
|
||||
`define MEM_DTIM 1
|
||||
`define MEM_DTIM 0
|
||||
`define MEM_DCACHE 0
|
||||
`define MEM_IROM 1
|
||||
`define MEM_IROM 0
|
||||
`define MEM_ICACHE 0
|
||||
`define MEM_VIRTMEM 0
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
|
1024
pipelined/config/rv32tim/BTBPredictor.txt
Normal file
1024
pipelined/config/rv32tim/BTBPredictor.txt
Normal file
File diff suppressed because it is too large
Load Diff
1024
pipelined/config/rv32tim/twoBitPredictor.txt
Normal file
1024
pipelined/config/rv32tim/twoBitPredictor.txt
Normal file
File diff suppressed because it is too large
Load Diff
133
pipelined/config/rv32tim/wally-config.vh
Normal file
133
pipelined/config/rv32tim/wally-config.vh
Normal file
@ -0,0 +1,133 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
|
||||
`define FPGA 0
|
||||
`define QEMU 0
|
||||
`define BUILDROOT 0
|
||||
`define BUSYBEAR 0
|
||||
`define DESIGN_COMPILER 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 32
|
||||
|
||||
// IEEE 754 compliance
|
||||
`define IEEE754 0
|
||||
|
||||
`define MISA (32'h00000104)
|
||||
`define ZICSR_SUPPORTED 1
|
||||
`define ZIFENCEI_SUPPORTED 0
|
||||
`define COUNTERS 32
|
||||
`define ZICOUNTERS_SUPPORTED 0
|
||||
|
||||
// Microarchitectural Features
|
||||
`define UARCH_PIPELINED 1
|
||||
`define UARCH_SUPERSCALR 0
|
||||
`define UARCH_SINGLECYCLE 0
|
||||
`define MEM_DTIM 1
|
||||
`define MEM_DCACHE 0
|
||||
`define MEM_IROM 1
|
||||
`define MEM_ICACHE 0
|
||||
`define MEM_VIRTMEM 0
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
`define ITLB_ENTRIES 0
|
||||
`define DTLB_ENTRIES 0
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
`define DCACHE_NUMWAYS 4
|
||||
`define DCACHE_WAYSIZEINBYTES 4096
|
||||
`define DCACHE_LINELENINBITS 256
|
||||
`define DCACHE_REPLBITS 3
|
||||
`define ICACHE_NUMWAYS 4
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_LINELENINBITS 256
|
||||
|
||||
// Integer Divider Configuration
|
||||
// DIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define DIV_BITSPERCYCLE 4
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 0
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 32'h80000000
|
||||
|
||||
// Peripheral Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
`define BOOTROM_SUPPORTED 1'b1
|
||||
`define BOOTROM_BASE 34'h00001000
|
||||
`define BOOTROM_RANGE 34'h00000FFF
|
||||
`define RAM_SUPPORTED 1'b1
|
||||
`define RAM_BASE 34'h80000000
|
||||
`define RAM_RANGE 34'h07FFFFFF
|
||||
`define EXT_MEM_SUPPORTED 1'b0
|
||||
`define EXT_MEM_BASE 34'h80000000
|
||||
`define EXT_MEM_RANGE 34'h07FFFFFF
|
||||
`define CLINT_SUPPORTED 1'b1
|
||||
`define CLINT_BASE 34'h02000000
|
||||
`define CLINT_RANGE 34'h0000FFFF
|
||||
`define GPIO_SUPPORTED 1'b1
|
||||
`define GPIO_BASE 34'h10012000
|
||||
`define GPIO_RANGE 34'h000000FF
|
||||
`define UART_SUPPORTED 1'b1
|
||||
`define UART_BASE 34'h10000000
|
||||
`define UART_RANGE 34'h00000007
|
||||
`define PLIC_SUPPORTED 1'b1
|
||||
`define PLIC_BASE 34'h0C000000
|
||||
`define PLIC_RANGE 34'h03FFFFFF
|
||||
`define SDC_SUPPORTED 1'b0
|
||||
`define SDC_BASE 34'h00012100
|
||||
`define SDC_RANGE 34'h0000001F
|
||||
|
||||
// Bus Interface width
|
||||
`define AHBW 32
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
`define GPIO_LOOPBACK_TEST 1
|
||||
|
||||
// Hardware configuration
|
||||
`define UART_PRESCALE 1
|
||||
|
||||
// Interrupt configuration
|
||||
`define PLIC_NUM_SRC 4
|
||||
// comment out the following if >=32 sources
|
||||
`define PLIC_NUM_SRC_LT_32
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 4
|
||||
|
||||
`define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt"
|
||||
`define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt"
|
||||
`define BPRED_ENABLED 1
|
||||
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define TESTSBP 0
|
@ -51,9 +51,9 @@
|
||||
`define UARCH_PIPELINED 1
|
||||
`define UARCH_SUPERSCALR 0
|
||||
`define UARCH_SINGLECYCLE 0
|
||||
`define MEM_DTIM 1
|
||||
`define MEM_DTIM 0
|
||||
`define MEM_DCACHE 1
|
||||
`define MEM_IROM 1
|
||||
`define MEM_IROM 0
|
||||
`define MEM_ICACHE 1
|
||||
`define MEM_VIRTMEM 1
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
|
@ -50,9 +50,9 @@
|
||||
`define UARCH_PIPELINED 1
|
||||
`define UARCH_SUPERSCALR 0
|
||||
`define UARCH_SINGLECYCLE 0
|
||||
`define MEM_DTIM 1
|
||||
`define MEM_DTIM 0
|
||||
`define MEM_DCACHE 1
|
||||
`define MEM_IROM 1
|
||||
`define MEM_IROM 0
|
||||
`define MEM_ICACHE 1
|
||||
`define MEM_VIRTMEM 1
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
|
@ -50,9 +50,9 @@
|
||||
`define UARCH_PIPELINED 1
|
||||
`define UARCH_SUPERSCALR 0
|
||||
`define UARCH_SINGLECYCLE 0
|
||||
`define MEM_DTIM 1
|
||||
`define MEM_DTIM 0
|
||||
`define MEM_DCACHE 1
|
||||
`define MEM_IROM 1
|
||||
`define MEM_IROM 0
|
||||
`define MEM_ICACHE 1
|
||||
`define MEM_VIRTMEM 1
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
|
@ -77,6 +77,15 @@ for test in tests32ic:
|
||||
grepstr="All tests ran without failures")
|
||||
configs.append(tc)
|
||||
|
||||
tests32tim = ["arch32i", "arch32c"]
|
||||
for test in tests32tim:
|
||||
tc = TestCase(
|
||||
name=test,
|
||||
variant="rv32tim",
|
||||
cmd="vsim > {} -c <<!\ndo wally-pipelined-tim-batch.do rv32tim "+test+"\n!",
|
||||
grepstr="All tests ran without failures")
|
||||
configs.append(tc)
|
||||
|
||||
|
||||
import os
|
||||
from multiprocessing import Pool, TimeoutError
|
||||
|
56
pipelined/regression/wally-harvard.do
Normal file
56
pipelined/regression/wally-harvard.do
Normal file
@ -0,0 +1,56 @@
|
||||
# wally-pipelined.do
|
||||
#
|
||||
# Modification by Oklahoma State University & Harvey Mudd College
|
||||
# Use with Testbench
|
||||
# James Stine, 2008; David Harris 2021
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# Takes 1:10 to run RV64IC tests using gui
|
||||
|
||||
# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m"
|
||||
|
||||
# Use this wally-pipelined.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do wally-pipelined.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do wally-pipelined.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work] {
|
||||
vdel -all
|
||||
}
|
||||
vlib work
|
||||
|
||||
# compile source files
|
||||
# suppress spurious warnngs about
|
||||
# "Extra checking for conflicts with always_comb done at vopt time"
|
||||
# because vsim will run vopt
|
||||
|
||||
# default to config/rv64ic, but allow this to be overridden at the command line. For example:
|
||||
# do wally-pipelined.do ../config/rv32ic
|
||||
#switch $argc {
|
||||
# 0 {vlog +incdir+../config/rv64ic +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
|
||||
# 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
|
||||
#}
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-harvard.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
|
||||
vopt +acc work.testbench -G TEST=$2 -o workopt
|
||||
vsim workopt
|
||||
|
||||
view wave
|
||||
-- display input and output signals as hexidecimal values
|
||||
#do ./wave-dos/peripheral-waves.do
|
||||
add log -recursive /*
|
||||
do wave.do
|
||||
|
||||
-- Run the Simulation
|
||||
#run 3600
|
||||
run -all
|
||||
#quit
|
||||
#noview ../testbench/testbench-imperas.sv
|
||||
noview ../testbench/testbench.sv
|
||||
view wave
|
50
pipelined/regression/wally-pipelined-tim-batch.do
Normal file
50
pipelined/regression/wally-pipelined-tim-batch.do
Normal file
@ -0,0 +1,50 @@
|
||||
# wally-pipelined-batch.do
|
||||
#
|
||||
# Modification by Oklahoma State University & Harvey Mudd College
|
||||
# Use with Testbench
|
||||
# James Stine, 2008; David Harris 2021
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# Takes 1:10 to run RV64IC tests using gui
|
||||
|
||||
# Usage: do wally-pipelined-batch.do <config> <testcases>
|
||||
# Example: do wally-pipelined-batch.do rv32ic imperas-32i
|
||||
|
||||
# Use this wally-pipelined-batch.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do wally-pipelined-batch.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do wally-pipelined-batch.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work_${1}_${2}] {
|
||||
vdel -lib work_${1}_${2} -all
|
||||
}
|
||||
vlib work_${1}_${2}
|
||||
|
||||
# compile source files
|
||||
# suppress spurious warnngs about
|
||||
# "Extra checking for conflicts with always_comb done at vopt time"
|
||||
# because vsim will run vopt
|
||||
|
||||
# default to config/rv64ic, but allow this to be overridden at the command line. For example:
|
||||
# do wally-pipelined-batch.do ../config/rv32ic rv32ic
|
||||
vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-tim.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
|
||||
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
vopt work_${1}_${2}.testbench -work work_${1}_${2} -G TEST=$2 -o testbenchopt
|
||||
vsim -lib work_${1}_${2} testbenchopt
|
||||
# Adding coverage increases runtime from 2:00 to 4:29. Can't run it all the time
|
||||
#vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf
|
||||
#vsim -coverage -lib work_$2 workopt_$2
|
||||
|
||||
run -all
|
||||
#coverage report -file wally-pipelined-coverage.txt
|
||||
# These aren't doing anything helpful
|
||||
#coverage report -memory
|
||||
#profile report -calltree -file wally-pipelined-calltree.rpt -cutoff 2
|
||||
quit
|
56
pipelined/regression/wally-pipelined-tim.do
Normal file
56
pipelined/regression/wally-pipelined-tim.do
Normal file
@ -0,0 +1,56 @@
|
||||
# wally-pipelined.do
|
||||
#
|
||||
# Modification by Oklahoma State University & Harvey Mudd College
|
||||
# Use with Testbench
|
||||
# James Stine, 2008; David Harris 2021
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# Takes 1:10 to run RV64IC tests using gui
|
||||
|
||||
# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m"
|
||||
|
||||
# Use this wally-pipelined.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do wally-pipelined.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do wally-pipelined.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work] {
|
||||
vdel -all
|
||||
}
|
||||
vlib work
|
||||
|
||||
# compile source files
|
||||
# suppress spurious warnngs about
|
||||
# "Extra checking for conflicts with always_comb done at vopt time"
|
||||
# because vsim will run vopt
|
||||
|
||||
# default to config/rv64ic, but allow this to be overridden at the command line. For example:
|
||||
# do wally-pipelined.do ../config/rv32ic
|
||||
#switch $argc {
|
||||
# 0 {vlog +incdir+../config/rv64ic +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
|
||||
# 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
|
||||
#}
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-tim.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
|
||||
vopt +acc work.testbench -G TEST=$2 -o workopt
|
||||
vsim workopt
|
||||
|
||||
view wave
|
||||
-- display input and output signals as hexidecimal values
|
||||
#do ./wave-dos/peripheral-waves.do
|
||||
add log -recursive /*
|
||||
do wave.do
|
||||
|
||||
-- Run the Simulation
|
||||
#run 3600
|
||||
run -all
|
||||
#quit
|
||||
#noview ../testbench/testbench-imperas.sv
|
||||
noview ../testbench/testbench.sv
|
||||
view wave
|
80
pipelined/src/generic/flop/simpleram.sv
Normal file
80
pipelined/src/generic/flop/simpleram.sv
Normal file
@ -0,0 +1,80 @@
|
||||
///////////////////////////////////////////
|
||||
// simpleram.sv
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 9 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: On-chip SIMPLERAM, external to hart
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// MIT LICENSE
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this
|
||||
// software and associated documentation files (the "Software"), to deal in the Software
|
||||
// without restriction, including without limitation the rights to use, copy, modify, merge,
|
||||
// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
|
||||
// to whom the Software is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or
|
||||
// substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
|
||||
// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
|
||||
// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
|
||||
// OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module simpleram #(parameter BASE=0, RANGE = 65535) (
|
||||
input logic HCLK, HRESETn,
|
||||
input logic HSELRam,
|
||||
input logic [31:0] HADDR,
|
||||
input logic HWRITE,
|
||||
input logic HREADY,
|
||||
input logic [1:0] HTRANS,
|
||||
input logic [`XLEN-1:0] HWDATA,
|
||||
output logic [`XLEN-1:0] HREADRam,
|
||||
output logic HRESPRam, HREADYRam
|
||||
);
|
||||
|
||||
localparam MemStartAddr = BASE>>(1+`XLEN/32);
|
||||
localparam MemEndAddr = (RANGE+BASE)>>1+(`XLEN/32);
|
||||
|
||||
logic [`XLEN-1:0] RAM[BASE>>(1+`XLEN/32):(RANGE+BASE)>>1+(`XLEN/32)];
|
||||
logic [31:0] HWADDR, A;
|
||||
logic [`XLEN-1:0] HREADRam0;
|
||||
|
||||
logic prevHREADYRam, risingHREADYRam;
|
||||
logic initTrans;
|
||||
logic memwrite;
|
||||
logic [3:0] busycount;
|
||||
|
||||
|
||||
/* verilator lint_off WIDTH */
|
||||
if (`XLEN == 64) begin:ramrw
|
||||
always_ff @(posedge HCLK) begin
|
||||
if (HWRITE & |HTRANS) RAM[HADDR[31:3]] <= #1 HWDATA;
|
||||
end
|
||||
end else begin
|
||||
always_ff @(posedge HCLK) begin:ramrw
|
||||
if (HWRITE & |HTRANS) RAM[HADDR[31:2]] <= #1 HWDATA;
|
||||
end
|
||||
end
|
||||
|
||||
// read
|
||||
if(`XLEN == 64) begin: ramr
|
||||
assign HREADRam0 = RAM[HADDR[31:3]];
|
||||
end else begin
|
||||
assign HREADRam0 = RAM[HADDR[31:2]];
|
||||
end
|
||||
|
||||
/* verilator lint_on WIDTH */
|
||||
|
||||
assign HREADRam = HREADRam0;
|
||||
endmodule
|
||||
|
@ -96,7 +96,7 @@ module ifu (
|
||||
logic [`XLEN-1:0] PCD;
|
||||
|
||||
localparam [31:0] nop = 32'h00000013; // instruction for NOP
|
||||
logic reset_q; // *** look at this later.
|
||||
//logic reset_q; // see comment below about PCNextF and icache.
|
||||
|
||||
logic BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
|
||||
logic [`XLEN-1:0] PCBPWrongInvalidate;
|
||||
@ -118,64 +118,64 @@ module ifu (
|
||||
logic [31:0] PostSpillInstrRawF;
|
||||
|
||||
|
||||
if(`C_SUPPORTED) begin : SpillSupport
|
||||
logic [`XLEN-1:0] PCFp2;
|
||||
logic Spill;
|
||||
logic SelSpill, SpillSave;
|
||||
logic [15:0] SpillDataLine0;
|
||||
if(`C_SUPPORTED) begin : SpillSupport
|
||||
logic [`XLEN-1:0] PCFp2;
|
||||
logic Spill;
|
||||
logic SelSpill, SpillSave;
|
||||
logic [15:0] SpillDataLine0;
|
||||
|
||||
// this exists only if there are compressed instructions.
|
||||
assign PCFp2 = PCF + `XLEN'b10;
|
||||
|
||||
assign PCNextFMux = SelNextSpill ? PCFp2[11:0] : PCNextF[11:0];
|
||||
assign PCFMux = SelSpill ? PCFp2 : PCF;
|
||||
|
||||
assign Spill = &PCF[$clog2(SPILLTHRESHOLD)+1:1];
|
||||
// this exists only if there are compressed instructions.
|
||||
assign PCFp2 = PCF + `XLEN'b10;
|
||||
|
||||
assign PCNextFMux = SelNextSpill ? PCFp2[11:0] : PCNextF[11:0];
|
||||
assign PCFMux = SelSpill ? PCFp2 : PCF;
|
||||
|
||||
assign Spill = &PCF[$clog2(SPILLTHRESHOLD)+1:1];
|
||||
|
||||
typedef enum {STATE_SPILL_READY, STATE_SPILL_SPILL} statetype;
|
||||
(* mark_debug = "true" *) statetype CurrState, NextState;
|
||||
typedef enum {STATE_SPILL_READY, STATE_SPILL_SPILL} statetype;
|
||||
(* mark_debug = "true" *) statetype CurrState, NextState;
|
||||
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (reset) CurrState <= #1 STATE_SPILL_READY;
|
||||
else CurrState <= #1 NextState;
|
||||
always_ff @(posedge clk)
|
||||
if (reset) CurrState <= #1 STATE_SPILL_READY;
|
||||
else CurrState <= #1 NextState;
|
||||
|
||||
always_comb begin
|
||||
case(CurrState)
|
||||
STATE_SPILL_READY: if (Spill & ~(ICacheStallF | BusStall)) NextState = STATE_SPILL_SPILL;
|
||||
else NextState = STATE_SPILL_READY;
|
||||
STATE_SPILL_SPILL: if(ICacheStallF | BusStall | StallF) NextState = STATE_SPILL_SPILL;
|
||||
else NextState = STATE_SPILL_READY;
|
||||
default: NextState = STATE_SPILL_READY;
|
||||
endcase
|
||||
end
|
||||
|
||||
assign SelSpill = CurrState == STATE_SPILL_SPILL;
|
||||
assign SelNextSpill = (CurrState == STATE_SPILL_READY & (Spill & ~(ICacheStallF | BusStall))) |
|
||||
(CurrState == STATE_SPILL_SPILL & (ICacheStallF | BusStall));
|
||||
assign SpillSave = CurrState == STATE_SPILL_READY & (Spill & ~(ICacheStallF | BusStall));
|
||||
|
||||
|
||||
flopenr #(16) SpillInstrReg(.clk(clk),
|
||||
.en(SpillSave),
|
||||
.reset(reset),
|
||||
.d(`MEM_ICACHE ? InstrRawF[15:0] : InstrRawF[31:16]),
|
||||
.q(SpillDataLine0));
|
||||
|
||||
assign PostSpillInstrRawF = Spill ? {InstrRawF[15:0], SpillDataLine0} : InstrRawF;
|
||||
assign CompressedF = PostSpillInstrRawF[1:0] != 2'b11;
|
||||
|
||||
// end of spill support
|
||||
end else begin : NoSpillSupport // line: SpillSupport
|
||||
assign PCNextFMux = PCNextF[11:0];
|
||||
assign PCFMux = PCF;
|
||||
assign SelNextSpill = 0;
|
||||
assign PostSpillInstrRawF = InstrRawF;
|
||||
always_comb begin
|
||||
case(CurrState)
|
||||
STATE_SPILL_READY: if (Spill & ~(ICacheStallF | BusStall)) NextState = STATE_SPILL_SPILL;
|
||||
else NextState = STATE_SPILL_READY;
|
||||
STATE_SPILL_SPILL: if(ICacheStallF | BusStall | StallF) NextState = STATE_SPILL_SPILL;
|
||||
else NextState = STATE_SPILL_READY;
|
||||
default: NextState = STATE_SPILL_READY;
|
||||
endcase
|
||||
end
|
||||
|
||||
assign SelSpill = CurrState == STATE_SPILL_SPILL;
|
||||
assign SelNextSpill = (CurrState == STATE_SPILL_READY & (Spill & ~(ICacheStallF | BusStall))) |
|
||||
(CurrState == STATE_SPILL_SPILL & (ICacheStallF | BusStall));
|
||||
assign SpillSave = CurrState == STATE_SPILL_READY & (Spill & ~(ICacheStallF | BusStall));
|
||||
|
||||
|
||||
flopenr #(16) SpillInstrReg(.clk(clk),
|
||||
.en(SpillSave),
|
||||
.reset(reset),
|
||||
.d(`MEM_ICACHE ? InstrRawF[15:0] : InstrRawF[31:16]),
|
||||
.q(SpillDataLine0));
|
||||
|
||||
assign PostSpillInstrRawF = Spill ? {InstrRawF[15:0], SpillDataLine0} : InstrRawF;
|
||||
assign CompressedF = PostSpillInstrRawF[1:0] != 2'b11;
|
||||
|
||||
// end of spill support
|
||||
end else begin : NoSpillSupport // line: SpillSupport
|
||||
assign PCNextFMux = PCNextF[11:0];
|
||||
assign PCFMux = PCF;
|
||||
assign SelNextSpill = 0;
|
||||
assign PostSpillInstrRawF = InstrRawF;
|
||||
end
|
||||
|
||||
|
||||
assign PCFExt = {2'b00, PCFMux};
|
||||
//
|
||||
|
||||
mmu #(.TLB_ENTRIES(`ITLB_ENTRIES), .IMMU(1))
|
||||
immu(.PAdr(PCFExt[`PA_BITS-1:0]),
|
||||
.VAdr(PCFMux),
|
||||
@ -206,25 +206,14 @@ module ifu (
|
||||
.PMPADDR_ARRAY_REGW
|
||||
);
|
||||
|
||||
|
||||
|
||||
// branch predictor signal
|
||||
logic SelBPPredF;
|
||||
logic [`XLEN-1:0] BPPredPCF, PCNext0F, PCNext1F, PCNext2F, PCNext3F;
|
||||
logic [4:0] InstrClassD, InstrClassE;
|
||||
|
||||
|
||||
|
||||
// *** put memory interface on here, InstrF becomes output
|
||||
//assign ICacheBusAdr = PCF; // *** no MMU
|
||||
//assign IFUBusFetch = ~StallD; // *** & ICacheMissF; add later
|
||||
// assign IFUBusFetch = 1; // *** & ICacheMissF; add later
|
||||
|
||||
// conditional
|
||||
// 1. ram // controlled by `MEM_IROM
|
||||
// 2. cache // `MEM_ICACHE
|
||||
// 3. wire pass-through
|
||||
|
||||
// If we have `MEM_IROM we don't have the bus controller
|
||||
// otherwise we have the bus controller and either a cache or a passthrough.
|
||||
|
||||
localparam integer WORDSPERLINE = `MEM_ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1;
|
||||
localparam integer SPILLTHRESHOLD = `MEM_ICACHE ? `ICACHE_LINELENINBITS/32 : 1;
|
||||
localparam integer LOGWPL = `MEM_ICACHE ? $clog2(WORDSPERLINE) : 1;
|
||||
@ -235,47 +224,94 @@ module ifu (
|
||||
localparam integer OFFSETLEN = $clog2(LINEBYTELEN);
|
||||
|
||||
logic [LOGWPL-1:0] WordCount;
|
||||
logic [LINELEN-1:0] ICacheMemWriteData;
|
||||
logic [LINELEN-1:0] ICacheMemWriteData;
|
||||
logic ICacheBusAck;
|
||||
logic [`PA_BITS-1:0] LocalIFUBusAdr;
|
||||
logic [`PA_BITS-1:0] ICacheBusAdr;
|
||||
logic SelUncachedAdr;
|
||||
|
||||
if(`MEM_ICACHE) begin : icache
|
||||
logic [1:0] IFURWF;
|
||||
assign IFURWF = CacheableF ? 2'b10 : 2'b00;
|
||||
|
||||
logic [`XLEN-1:0] FinalInstrRawF_FIXME;
|
||||
|
||||
cache #(.LINELEN(`ICACHE_LINELENINBITS),
|
||||
.NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
|
||||
.NUMWAYS(`ICACHE_NUMWAYS), .DCACHE(0))
|
||||
icache(.clk, .reset, .CPUBusy, .IgnoreRequest, .CacheMemWriteData(ICacheMemWriteData) , .CacheBusAck(ICacheBusAck),
|
||||
.CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), .ReadDataWord(FinalInstrRawF_FIXME),
|
||||
.CacheFetchLine(ICacheFetchLine),
|
||||
.CacheWriteLine(),
|
||||
.ReadDataLineSets(),
|
||||
.CacheMiss(ICacheMiss),
|
||||
.CacheAccess(ICacheAccess),
|
||||
.FinalWriteData('0),
|
||||
.RW(IFURWF),
|
||||
.Atomic(2'b00),
|
||||
.FlushCache(1'b0),
|
||||
.NextAdr(PCNextFMux),
|
||||
.PAdr(PCPF),
|
||||
.CacheCommitted(),
|
||||
.InvalidateCacheM(InvalidateICacheM));
|
||||
if (`MEM_IROM) begin : irom
|
||||
logic [`XLEN-1:0] FinalInstrRawF_FIXME;
|
||||
|
||||
assign FinalInstrRawF = FinalInstrRawF_FIXME[31:0];
|
||||
end else begin
|
||||
assign ICacheFetchLine = 0;
|
||||
assign ICacheBusAdr = 0;
|
||||
assign ICacheStallF = 0;
|
||||
assign FinalInstrRawF = 0;
|
||||
assign ICacheAccess = CacheableF;
|
||||
assign ICacheMiss = CacheableF;
|
||||
end
|
||||
simpleram #(
|
||||
.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
|
||||
.HCLK(clk), .HRESETn(~reset),
|
||||
.HSELRam(1'b1), .HADDR(PCPF[31:0]),
|
||||
.HWRITE(1'b0), .HREADY(1'b1),
|
||||
.HTRANS(2'b10), .HWDATA(0), .HREADRam(FinalInstrRawF_FIXME),
|
||||
.HRESPRam(), .HREADYRam());
|
||||
|
||||
assign FinalInstrRawF = FinalInstrRawF_FIXME[31:0];
|
||||
assign BusStall = 0;
|
||||
assign IFUBusRead = 0;
|
||||
assign ICacheBusAck = 0;
|
||||
assign SelUncachedAdr = 0;
|
||||
assign IFUBusAdr = 0;
|
||||
|
||||
|
||||
end else begin : bus
|
||||
genvar index;
|
||||
for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
|
||||
flopen #(`XLEN) fb(.clk(clk),
|
||||
.en(IFUBusAck & IFUBusRead & (index == WordCount)),
|
||||
.d(IFUBusHRDATA),
|
||||
.q(ICacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN]));
|
||||
end
|
||||
|
||||
assign LocalIFUBusAdr = SelUncachedAdr ? PCPF : ICacheBusAdr;
|
||||
assign IFUBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalIFUBusAdr;
|
||||
|
||||
busfsm #(WordCountThreshold, LOGWPL, `MEM_ICACHE)
|
||||
busfsm(.clk, .reset, .IgnoreRequest,
|
||||
.LSURWM(2'b10), .DCacheFetchLine(ICacheFetchLine), .DCacheWriteLine(1'b0),
|
||||
.LSUBusAck(IFUBusAck),
|
||||
.CPUBusy, .CacheableM(CacheableF),
|
||||
.BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead), .DCacheBusAck(ICacheBusAck),
|
||||
.BusCommittedM(), .SelUncachedAdr(SelUncachedAdr), .WordCount);
|
||||
|
||||
end
|
||||
|
||||
if(`MEM_ICACHE) begin : icache
|
||||
logic [1:0] IFURWF;
|
||||
assign IFURWF = CacheableF ? 2'b10 : 2'b00;
|
||||
|
||||
logic [`XLEN-1:0] FinalInstrRawF_FIXME;
|
||||
|
||||
cache #(.LINELEN(`ICACHE_LINELENINBITS),
|
||||
.NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
|
||||
.NUMWAYS(`ICACHE_NUMWAYS), .DCACHE(0))
|
||||
icache(.clk, .reset, .CPUBusy, .IgnoreRequest, .CacheMemWriteData(ICacheMemWriteData) , .CacheBusAck(ICacheBusAck),
|
||||
.CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), .ReadDataWord(FinalInstrRawF_FIXME),
|
||||
.CacheFetchLine(ICacheFetchLine),
|
||||
.CacheWriteLine(),
|
||||
.ReadDataLineSets(),
|
||||
.CacheMiss(ICacheMiss),
|
||||
.CacheAccess(ICacheAccess),
|
||||
.FinalWriteData('0),
|
||||
.RW(IFURWF),
|
||||
.Atomic(2'b00),
|
||||
.FlushCache(1'b0),
|
||||
.NextAdr(PCNextFMux),
|
||||
.PAdr(PCPF),
|
||||
.CacheCommitted(),
|
||||
.InvalidateCacheM(InvalidateICacheM));
|
||||
|
||||
assign FinalInstrRawF = FinalInstrRawF_FIXME[31:0];
|
||||
end else begin
|
||||
assign ICacheFetchLine = 0;
|
||||
assign ICacheBusAdr = 0;
|
||||
assign ICacheStallF = 0;
|
||||
if(!`MEM_IROM) assign FinalInstrRawF = 0;
|
||||
assign ICacheAccess = CacheableF;
|
||||
assign ICacheMiss = CacheableF;
|
||||
end
|
||||
|
||||
// branch predictor signal
|
||||
logic SelBPPredF;
|
||||
logic [`XLEN-1:0] BPPredPCF, PCNext0F, PCNext1F, PCNext2F, PCNext3F;
|
||||
logic [4:0] InstrClassD, InstrClassE;
|
||||
|
||||
|
||||
// select between dcache and direct from the BUS. Always selected if no dcache.
|
||||
// handled in the busfsm.
|
||||
mux2 #(32) UnCachedInstrMux(.d0(FinalInstrRawF),
|
||||
@ -283,26 +319,6 @@ module ifu (
|
||||
.s(SelUncachedAdr),
|
||||
.y(InstrRawF));
|
||||
|
||||
// always present
|
||||
genvar index;
|
||||
for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
|
||||
flopen #(`XLEN) fb(.clk(clk),
|
||||
.en(IFUBusAck & IFUBusRead & (index == WordCount)),
|
||||
.d(IFUBusHRDATA),
|
||||
.q(ICacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN]));
|
||||
end
|
||||
|
||||
assign LocalIFUBusAdr = SelUncachedAdr ? PCPF : ICacheBusAdr;
|
||||
assign IFUBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalIFUBusAdr;
|
||||
|
||||
busfsm #(WordCountThreshold, LOGWPL, `MEM_ICACHE)
|
||||
busfsm(.clk, .reset, .IgnoreRequest,
|
||||
.LSURWM(2'b10), .DCacheFetchLine(ICacheFetchLine), .DCacheWriteLine(1'b0),
|
||||
.LSUBusAck(IFUBusAck),
|
||||
.CPUBusy, .CacheableM(CacheableF),
|
||||
.BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead), .DCacheBusAck(ICacheBusAck),
|
||||
.BusCommittedM(), .SelUncachedAdr(SelUncachedAdr), .WordCount);
|
||||
|
||||
assign IFUStallF = ICacheStallF | BusStall | SelNextSpill;
|
||||
assign CPUBusy = StallF & ~SelNextSpill;
|
||||
|
||||
@ -310,10 +326,8 @@ module ifu (
|
||||
// this is a difference with the dcache.
|
||||
// uses interlock fsm.
|
||||
assign IgnoreRequest = ITLBMissF;
|
||||
|
||||
|
||||
flopenl #(32) AlignedInstrRawDFlop(clk, reset | reset_q, ~StallD, FlushD ? nop : PostSpillInstrRawF, nop, InstrRawD);
|
||||
|
||||
flopenl #(32) AlignedInstrRawDFlop(clk, reset, ~StallD, FlushD ? nop : PostSpillInstrRawF, nop, InstrRawD);
|
||||
|
||||
assign PrivilegedChangePCM = RetM | TrapM;
|
||||
|
||||
@ -340,16 +354,26 @@ module ifu (
|
||||
mux2 #(`XLEN) pcmux3(.d0(PCNext2F),
|
||||
.d1(PrivilegedNextPCM),
|
||||
.s(PrivilegedChangePCM),
|
||||
.y(PCNext3F));
|
||||
.y(UnalignedPCNextF));
|
||||
|
||||
mux2 #(`XLEN) pcmux4(.d0(PCNext3F),
|
||||
.d1(`RESET_VECTOR),
|
||||
.s(reset_q),
|
||||
.y(UnalignedPCNextF));
|
||||
|
||||
flop #(1) resetReg (.clk(clk),
|
||||
.d(reset),
|
||||
.q(reset_q));
|
||||
//.y(PCNext3F));
|
||||
// This mux is not strictly speaking required. Because the icache takes in
|
||||
// PCNextF rather than PCPF, PCNextF should stay in reset while the cache
|
||||
// looks up the addresses. Without this mux PCNextF will increment + 2/4.
|
||||
// When the icache fsm is out of reset then it will report on the status
|
||||
// of PCF + 2/4. It will be a miss since this is the very first access.
|
||||
// On the next cycle the cache will start using PCPF to finish the read.
|
||||
// Because the granularity of a cache line +2/4 will always fit in the same
|
||||
// cache line so the mux is not required. I am leaving this comment and mux
|
||||
// a a reminder as to what is happening in case keep PCNextF at RESET_VECTOR
|
||||
// during reset becomes a requirement.
|
||||
//mux2 #(`XLEN) pcmux4(.d0(PCNext3F),
|
||||
// .d1(`RESET_VECTOR),
|
||||
// .s(reset_q),
|
||||
// .y(UnalignedPCNextF));
|
||||
//flop #(1) resetReg (.clk(clk),
|
||||
// .d(reset),
|
||||
// .q(reset_q));
|
||||
|
||||
|
||||
flopenrc #(1) BPPredWrongMReg(.clk, .reset, .en(~StallM), .clear(FlushM),
|
||||
@ -362,10 +386,10 @@ module ifu (
|
||||
|
||||
assign PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment
|
||||
// *** double check this enable. It cannot be correct.
|
||||
flopenl #(`XLEN) pcreg(clk, reset, ~StallF & ~ICacheStallF, PCNextF, `RESET_VECTOR, PCF);
|
||||
flopenl #(`XLEN) pcreg(clk, reset, ~StallF, PCNextF, `RESET_VECTOR, PCF);
|
||||
|
||||
// branch and jump predictor
|
||||
if (`BPRED_ENABLED == 1) begin : bpred
|
||||
if (`BPRED_ENABLED) begin : bpred
|
||||
bpred bpred(.clk, .reset,
|
||||
.StallF, .StallD, .StallE,
|
||||
.FlushF, .FlushD, .FlushE,
|
||||
|
@ -330,7 +330,7 @@ module lsu
|
||||
.CacheFetchLine(DCacheFetchLine), .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCacheM(1'b0));
|
||||
|
||||
end else begin : passthrough
|
||||
assign ReadDataWordM = 0;
|
||||
if(!`MEM_DTIM) assign ReadDataWordM = 0;
|
||||
assign DCacheStall = 0;
|
||||
assign DCacheMiss = CacheableM;
|
||||
assign DCacheAccess = CacheableM;
|
||||
@ -371,35 +371,56 @@ module lsu
|
||||
.HWDATAIN(FinalAMOWriteDataM),
|
||||
.HWDATA(FinalWriteDataM));
|
||||
|
||||
// Bus Side logic
|
||||
// register the fetch data from the next level of memory.
|
||||
// This register should be necessary for timing. There is no register in the uncore or
|
||||
// ahblite controller between the memories and this cache.
|
||||
logic [LOGWPL-1:0] WordCount;
|
||||
|
||||
genvar index;
|
||||
for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
|
||||
flopen #(`XLEN) fb(.clk,
|
||||
.en(LSUBusAck & LSUBusRead & (index == WordCount)),
|
||||
.d(LSUBusHRDATA),
|
||||
.q(DCacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN]));
|
||||
if (`MEM_DTIM == 1) begin : dtim
|
||||
simpleram #(
|
||||
.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
|
||||
.HCLK(clk), .HRESETn(~reset),
|
||||
.HSELRam(1'b1), .HADDR(LSUPAdrM[31:0]),
|
||||
.HWRITE(LSURWM[0]), .HREADY(1'b1),
|
||||
.HTRANS(|LSURWM ? 2'b10 : 2'b00), .HWDATA(FinalWriteDataM), .HREADRam(ReadDataWordM),
|
||||
.HRESPRam(), .HREADYRam());
|
||||
|
||||
// since we have a local memory the bus connections are all disabled.
|
||||
// There are no peripherals supported.
|
||||
assign BusStall = 0;
|
||||
assign LSUBusWrite = 0;
|
||||
assign LSUBusRead = 0;
|
||||
assign DCacheBusAck = 0;
|
||||
assign BusCommittedM = 0;
|
||||
assign SelUncachedAdr = 0;
|
||||
|
||||
end else begin : bus
|
||||
// Bus Side logic
|
||||
// register the fetch data from the next level of memory.
|
||||
// This register should be necessary for timing. There is no register in the uncore or
|
||||
// ahblite controller between the memories and this cache.
|
||||
logic [LOGWPL-1:0] WordCount;
|
||||
|
||||
genvar index;
|
||||
for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
|
||||
flopen #(`XLEN) fb(.clk,
|
||||
.en(LSUBusAck & LSUBusRead & (index == WordCount)),
|
||||
.d(LSUBusHRDATA),
|
||||
.q(DCacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN]));
|
||||
end
|
||||
|
||||
assign LocalLSUBusAdr = SelUncachedAdr ? LSUPAdrM : DCacheBusAdr ;
|
||||
assign LSUBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalLSUBusAdr;
|
||||
assign PreLSUBusHWDATA = ReadDataLineSetsM[WordCount];
|
||||
// exclude the subword write for uncached. We don't read the data first so we cannot
|
||||
// select the subword by masking. Subword write also exists inside the uncore to
|
||||
// suport subword masking for i/o. I'm not sure if this is necessary.
|
||||
assign LSUBusHWDATA = SelUncachedAdr ? FinalAMOWriteDataM : PreLSUBusHWDATA;
|
||||
|
||||
if (`XLEN == 32) assign LSUBusSize = SelUncachedAdr ? LSUFunct3M : 3'b010;
|
||||
else assign LSUBusSize = SelUncachedAdr ? LSUFunct3M : 3'b011;
|
||||
|
||||
busfsm #(WordCountThreshold, LOGWPL, `MEM_DCACHE)
|
||||
busfsm(.clk, .reset, .IgnoreRequest, .LSURWM, .DCacheFetchLine, .DCacheWriteLine,
|
||||
.LSUBusAck, .CPUBusy, .CacheableM, .BusStall, .LSUBusWrite, .LSUBusRead,
|
||||
.DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount);
|
||||
end
|
||||
|
||||
assign LocalLSUBusAdr = SelUncachedAdr ? LSUPAdrM : DCacheBusAdr ;
|
||||
assign LSUBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalLSUBusAdr;
|
||||
assign PreLSUBusHWDATA = ReadDataLineSetsM[WordCount];
|
||||
// exclude the subword write for uncached. We don't read the data first so we cannot
|
||||
// select the subword by masking. Subword write also exists inside the uncore to
|
||||
// suport subword masking for i/o. I'm not sure if this is necessary.
|
||||
assign LSUBusHWDATA = SelUncachedAdr ? FinalAMOWriteDataM : PreLSUBusHWDATA;
|
||||
|
||||
if (`XLEN == 32) assign LSUBusSize = SelUncachedAdr ? LSUFunct3M : 3'b010;
|
||||
else assign LSUBusSize = SelUncachedAdr ? LSUFunct3M : 3'b011;
|
||||
|
||||
busfsm #(WordCountThreshold, LOGWPL, `MEM_DCACHE)
|
||||
busfsm(.clk, .reset, .IgnoreRequest, .LSURWM, .DCacheFetchLine, .DCacheWriteLine,
|
||||
.LSUBusAck, .CPUBusy, .CacheableM, .BusStall, .LSUBusWrite, .LSUBusRead,
|
||||
.DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount);
|
||||
|
||||
endmodule
|
||||
|
||||
|
@ -56,6 +56,8 @@ module ram #(parameter BASE=0, RANGE = 65535) (
|
||||
|
||||
if(`FPGA) begin:ram
|
||||
initial begin
|
||||
// *** need to address this preload for fpga. It should work as a preload file
|
||||
// but for some reason vivado is not synthesizing the preload.
|
||||
//$readmemh(PRELOAD, RAM);
|
||||
RAM[0] = 64'h94e1819300002197;
|
||||
RAM[1] = 64'h4281420141014081;
|
||||
|
2
pipelined/testbench/fp/case.sh
Executable file
2
pipelined/testbench/fp/case.sh
Executable file
@ -0,0 +1,2 @@
|
||||
#!/bin/sh
|
||||
sed -i 's/[A-Z]/\L&/g' $1
|
476
pipelined/testbench/testbench-tim.sv
Normal file
476
pipelined/testbench/testbench-tim.sv
Normal file
@ -0,0 +1,476 @@
|
||||
///////////////////////////////////////////
|
||||
// testbench.sv
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 9 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Wally Testbench and helper modules
|
||||
// Applies test programs from the riscv-arch-test and Imperas suites
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// MIT LICENSE
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this
|
||||
// software and associated documentation files (the "Software"), to deal in the Software
|
||||
// without restriction, including without limitation the rights to use, copy, modify, merge,
|
||||
// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
|
||||
// to whom the Software is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or
|
||||
// substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
|
||||
// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
|
||||
// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
|
||||
// OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
`include "tests.vh"
|
||||
|
||||
module testbench;
|
||||
parameter TESTSPERIPH = 0; // set to 0 for regression
|
||||
parameter TESTSPRIV = 0; // set to 0 for regression
|
||||
parameter DEBUG=0;
|
||||
parameter TEST="none";
|
||||
|
||||
logic clk;
|
||||
logic reset_ext, reset;
|
||||
|
||||
parameter SIGNATURESIZE = 5000000;
|
||||
|
||||
int test, i, errors, totalerrors;
|
||||
logic [31:0] sig32[0:SIGNATURESIZE];
|
||||
logic [`XLEN-1:0] signature[0:SIGNATURESIZE];
|
||||
logic [`XLEN-1:0] testadr;
|
||||
string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
|
||||
logic [31:0] InstrW;
|
||||
logic [`XLEN-1:0] meminit;
|
||||
|
||||
|
||||
string tests[];
|
||||
logic [3:0] dummy;
|
||||
|
||||
string ProgramAddrMapFile, ProgramLabelMapFile;
|
||||
logic [`AHBW-1:0] HRDATAEXT;
|
||||
logic HREADYEXT, HRESPEXT;
|
||||
logic [31:0] HADDR;
|
||||
logic [`AHBW-1:0] HWDATA;
|
||||
logic HWRITE;
|
||||
logic [2:0] HSIZE;
|
||||
logic [2:0] HBURST;
|
||||
logic [3:0] HPROT;
|
||||
logic [1:0] HTRANS;
|
||||
logic HMASTLOCK;
|
||||
logic HCLK, HRESETn;
|
||||
logic [`XLEN-1:0] PCW;
|
||||
|
||||
logic DCacheFlushDone, DCacheFlushStart;
|
||||
|
||||
flopenr #(`XLEN) PCWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.PCM, PCW);
|
||||
flopenr #(32) InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.InstrM, InstrW);
|
||||
|
||||
// check assertions for a legal configuration
|
||||
riscvassertions riscvassertions();
|
||||
|
||||
// pick tests based on modes supported
|
||||
initial begin
|
||||
$display("TEST is %s", TEST);
|
||||
//tests = '{};
|
||||
if (`XLEN == 64) begin // RV64
|
||||
case (TEST)
|
||||
"arch64i": tests = arch64i;
|
||||
"arch64priv": tests = arch64priv;
|
||||
"arch64c": if (`C_SUPPORTED)
|
||||
if (`ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv};
|
||||
else tests = {arch64c};
|
||||
"arch64m": if (`M_SUPPORTED) tests = arch64m;
|
||||
"arch64d": if (`D_SUPPORTED) tests = arch64d;
|
||||
"imperas64i": tests = imperas64i;
|
||||
"imperas64p": tests = imperas64p;
|
||||
// "imperas64mmu": if (`MEM_VIRTMEM) tests = imperas64mmu;
|
||||
"imperas64f": if (`F_SUPPORTED) tests = imperas64f;
|
||||
"imperas64d": if (`D_SUPPORTED) tests = imperas64d;
|
||||
"imperas64m": if (`M_SUPPORTED) tests = imperas64m;
|
||||
"imperas64a": if (`A_SUPPORTED) tests = imperas64a;
|
||||
"imperas64c": if (`C_SUPPORTED) tests = imperas64c;
|
||||
else tests = imperas64iNOc;
|
||||
"testsBP64": tests = testsBP64;
|
||||
"wally64i": tests = wally64i; // *** redo
|
||||
"wally64priv": tests = wally64priv;// *** redo
|
||||
"imperas64periph": tests = imperas64periph;
|
||||
endcase
|
||||
end else begin // RV32
|
||||
case (TEST)
|
||||
"arch32i": tests = arch32i;
|
||||
"arch32priv": tests = arch32priv;
|
||||
"arch32c": if (`C_SUPPORTED)
|
||||
if (`ZICSR_SUPPORTED) tests = {arch32c, arch32cpriv};
|
||||
else tests = {arch32c};
|
||||
"arch32m": if (`M_SUPPORTED) tests = arch32m;
|
||||
"arch32f": if (`F_SUPPORTED) tests = arch32f;
|
||||
"imperas32i": tests = imperas32i;
|
||||
"imperas32p": tests = imperas32p;
|
||||
// "imperas32mmu": if (`MEM_VIRTMEM) tests = imperas32mmu;
|
||||
"imperas32f": if (`F_SUPPORTED) tests = imperas32f;
|
||||
"imperas32m": if (`M_SUPPORTED) tests = imperas32m;
|
||||
"imperas32a": if (`A_SUPPORTED) tests = imperas32a;
|
||||
"imperas32c": if (`C_SUPPORTED) tests = imperas32c;
|
||||
else tests = imperas32iNOc;
|
||||
"wally32i": tests = wally32i; // *** redo
|
||||
"wally32priv": tests = wally32priv; // *** redo
|
||||
"imperas32periph": tests = imperas32periph;
|
||||
endcase
|
||||
end
|
||||
if (tests.size() == 0) begin
|
||||
$display("TEST %s not supported in this configuration", TEST);
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
|
||||
string signame, memfilename, pathname;
|
||||
|
||||
logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
|
||||
logic UARTSin, UARTSout;
|
||||
|
||||
logic SDCCLK;
|
||||
logic SDCCmdIn;
|
||||
logic SDCCmdOut;
|
||||
logic SDCCmdOE;
|
||||
logic [3:0] SDCDatIn;
|
||||
|
||||
logic HREADY;
|
||||
logic HSELEXT;
|
||||
|
||||
|
||||
// instantiate device to be tested
|
||||
assign GPIOPinsIn = 0;
|
||||
assign UARTSin = 1;
|
||||
assign HREADYEXT = 1;
|
||||
assign HRESPEXT = 0;
|
||||
assign HRDATAEXT = 0;
|
||||
|
||||
wallypipelinedsoc dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
|
||||
.HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT,
|
||||
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
|
||||
.UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK);
|
||||
|
||||
// Track names of instructions
|
||||
instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
|
||||
dut.hart.ifu.FinalInstrRawF,
|
||||
dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
|
||||
dut.hart.ifu.InstrM, InstrW,
|
||||
InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
|
||||
|
||||
// initialize tests
|
||||
localparam integer MemStartAddr = `RAM_BASE>>(1+`XLEN/32);
|
||||
localparam integer MemEndAddr = (`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32);
|
||||
|
||||
initial
|
||||
begin
|
||||
test = 1;
|
||||
totalerrors = 0;
|
||||
testadr = 0;
|
||||
// fill memory with defined values to reduce Xs in simulation
|
||||
// Quick note the memory will need to be initialized. The C library does not
|
||||
// guarantee the initialized reads. For example a strcmp can read 6 byte
|
||||
// strings, but uses a load double to read them in. If the last 2 bytes are
|
||||
// not initialized the compare results in an 'x' which propagates through
|
||||
// the design.
|
||||
if (`XLEN == 32) meminit = 32'hFEDC0123;
|
||||
else meminit = 64'hFEDCBA9876543210;
|
||||
// *** broken because DTIM also drives RAM
|
||||
if (`TESTSBP) begin
|
||||
for (i=MemStartAddr; i<MemEndAddr; i = i+1) begin
|
||||
dut.uncore.ram.ram.RAM[i] = meminit;
|
||||
end
|
||||
end
|
||||
// read test vectors into memory
|
||||
pathname = tvpaths[tests[0].atoi()];
|
||||
/* if (tests[0] == `IMPERASTEST)
|
||||
pathname = tvpaths[0];
|
||||
else pathname = tvpaths[1]; */
|
||||
memfilename = {pathname, tests[test], ".elf.memfile"};
|
||||
//$readmemh(memfilename, dut.uncore.ram.ram.RAM);
|
||||
$readmemh(memfilename, dut.hart.lsu.dtim.ram.RAM);
|
||||
// if(`MEM_DTIM == 1) $readmemh(memfilename, dut.hart.lsu.dtim.ram.RAM);
|
||||
//`ifdef `MEM_IROM
|
||||
// $display("here!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!");
|
||||
// $readmemh(memfilename, dut.hart.ifu.irom.ram.RAM);
|
||||
//`endif
|
||||
// if(`MEM_IROM == 1) begin
|
||||
// $display("here!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!");
|
||||
$readmemh(memfilename, dut.hart.ifu.irom.ram.RAM);
|
||||
// end
|
||||
ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
|
||||
ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
|
||||
$display("Read memfile %s", memfilename);
|
||||
reset_ext = 1; # 42; reset_ext = 0;
|
||||
end
|
||||
|
||||
// generate clock to sequence tests
|
||||
always
|
||||
begin
|
||||
clk = 1; # 5; clk = 0; # 5;
|
||||
// if ($time % 100000 == 0) $display("Time is %0t", $time);
|
||||
end
|
||||
|
||||
// check results
|
||||
always @(negedge clk)
|
||||
begin
|
||||
if (DCacheFlushDone) begin
|
||||
|
||||
#600; // give time for instructions in pipeline to finish
|
||||
// clear signature to prevent contamination from previous tests
|
||||
for(i=0; i<SIGNATURESIZE; i=i+1) begin
|
||||
sig32[i] = 'bx;
|
||||
end
|
||||
|
||||
// read signature, reformat in 64 bits if necessary
|
||||
signame = {pathname, tests[test], ".signature.output"};
|
||||
$readmemh(signame, sig32);
|
||||
i = 0;
|
||||
while (i < SIGNATURESIZE) begin
|
||||
if (`XLEN == 32) begin
|
||||
signature[i] = sig32[i];
|
||||
i = i+1;
|
||||
end else begin
|
||||
signature[i/2] = {sig32[i+1], sig32[i]};
|
||||
i = i + 2;
|
||||
end
|
||||
if (sig32[i-1] === 'bx) begin
|
||||
if (i == 1) begin
|
||||
i = SIGNATURESIZE+1; // flag empty file
|
||||
$display(" Error: empty test file");
|
||||
end else i = SIGNATURESIZE; // skip over the rest of the x's for efficiency
|
||||
end
|
||||
end
|
||||
|
||||
// Check errors
|
||||
errors = (i == SIGNATURESIZE+1); // error if file is empty
|
||||
i = 0;
|
||||
testadr = (`RAM_BASE+tests[test+1].atohex())/(`XLEN/8);
|
||||
/* verilator lint_off INFINITELOOP */
|
||||
while (signature[i] !== 'bx) begin
|
||||
//$display("signature[%h] = %h", i, signature[i]);
|
||||
// *** have to figure out how to exclude shadowram when not using a dcache.
|
||||
if (signature[i] !== dut.hart.lsu.dtim.ram.RAM[testadr+i] &
|
||||
(signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin
|
||||
if (signature[i+4] !== 'bx | signature[i] !== 32'hFFFFFFFF) begin
|
||||
// report errors unless they are garbage at the end of the sim
|
||||
// kind of hacky test for garbage right now
|
||||
errors = errors+1;
|
||||
$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (TIM) = %h, signature = %h",
|
||||
//tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dut.uncore.ram.ram.RAM[testadr+i], signature[i]);
|
||||
tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dut.hart.lsu.dtim.ram.RAM[testadr+i], signature[i]);
|
||||
$stop;//***debug
|
||||
end
|
||||
end
|
||||
i = i + 1;
|
||||
end
|
||||
/* verilator lint_on INFINITELOOP */
|
||||
if (errors == 0) begin
|
||||
$display("%s succeeded. Brilliant!!!", tests[test]);
|
||||
end
|
||||
else begin
|
||||
$display("%s failed with %d errors. :(", tests[test], errors);
|
||||
totalerrors = totalerrors+1;
|
||||
end
|
||||
test = test + 2;
|
||||
if (test == tests.size()) begin
|
||||
if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
|
||||
else $display("FAIL: %d test programs had errors", totalerrors);
|
||||
$stop;
|
||||
end
|
||||
else begin
|
||||
//pathname = tvpaths[tests[0]];
|
||||
memfilename = {pathname, tests[test], ".elf.memfile"};
|
||||
//$readmemh(memfilename, dut.uncore.ram.ram.RAM);
|
||||
$readmemh(memfilename, dut.hart.lsu.dtim.ram.RAM);
|
||||
//if(`MEM_DTIM == 1) $readmemh(memfilename, dut.hart.lsu.dtim.ram.RAM);
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
`ifdef `MEM_IROM
|
||||
$display("here!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!");
|
||||
$readmemh(memfilename, dut.hart.ifu.irom.ram.RAM);
|
||||
`endif
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
$readmemh(memfilename, dut.hart.ifu.irom.ram.RAM);
|
||||
//if(`MEM_IROM == 1) $readmemh(memfilename, dut.hart.ifu.irom.ram.RAM);
|
||||
ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
|
||||
ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
|
||||
$display("Read memfile %s", memfilename);
|
||||
reset_ext = 1; # 47; reset_ext = 0;
|
||||
end
|
||||
end
|
||||
end // always @ (negedge clk)
|
||||
|
||||
// track the current function or global label
|
||||
if (DEBUG == 1) begin : FunctionName
|
||||
FunctionName FunctionName(.reset(reset),
|
||||
.clk(clk),
|
||||
.ProgramAddrMapFile(ProgramAddrMapFile),
|
||||
.ProgramLabelMapFile(ProgramLabelMapFile));
|
||||
end
|
||||
|
||||
// Termination condition
|
||||
// terminate on a specific ECALL after li x3,1 for old Imperas tests, *** remove this when old imperas tests are removed
|
||||
// or sw gp,-56(t0) for new Imperas tests
|
||||
// or sd gp, -56(t0)
|
||||
// or on a jump to self infinite loop (6f) for RISC-V Arch tests
|
||||
logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls
|
||||
if (`ZICSR_SUPPORTED) assign ecf = dut.hart.priv.priv.EcallFaultM;
|
||||
else assign ecf = 0;
|
||||
assign DCacheFlushStart = ecf &
|
||||
(dut.hart.ieu.dp.regf.rf[3] == 1 |
|
||||
(dut.hart.ieu.dp.regf.we3 &
|
||||
dut.hart.ieu.dp.regf.a3 == 3 &
|
||||
dut.hart.ieu.dp.regf.wd3 == 1)) |
|
||||
(dut.hart.ifu.InstrM == 32'h6f | dut.hart.ifu.InstrM == 32'hfc32a423 | dut.hart.ifu.InstrM == 32'hfc32a823) & dut.hart.ieu.c.InstrValidM;
|
||||
|
||||
DCacheFlushFSM DCacheFlushFSM(.clk(clk),
|
||||
.reset(reset),
|
||||
.start(DCacheFlushStart),
|
||||
.done(DCacheFlushDone));
|
||||
|
||||
// initialize the branch predictor
|
||||
if (`BPRED_ENABLED == 1)
|
||||
initial begin
|
||||
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
|
||||
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.mem);
|
||||
end
|
||||
endmodule
|
||||
|
||||
module riscvassertions;
|
||||
initial begin
|
||||
assert (`PMP_ENTRIES == 0 | `PMP_ENTRIES==16 | `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
|
||||
assert (`S_SUPPORTED | `MEM_VIRTMEM == 0) else $error("Virtual memory requires S mode support");
|
||||
assert (`DIV_BITSPERCYCLE == 1 | `DIV_BITSPERCYCLE==2 | `DIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: DIV_BITSPERCYCLE must be 1, 2, or 4");
|
||||
assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double (D) without supporting float (F)");
|
||||
assert (`XLEN == 64 | ~`D_SUPPORTED) else $error("Wally does not yet support D extensions on RV32");
|
||||
assert (`DCACHE_WAYSIZEINBYTES <= 4096 | `MEM_DCACHE == 0 | `MEM_VIRTMEM == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||
assert (`DCACHE_LINELENINBITS >= 128 | `MEM_DCACHE == 0) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
|
||||
assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size");
|
||||
assert (`ICACHE_WAYSIZEINBYTES <= 4096 | `MEM_ICACHE == 0 | `MEM_VIRTMEM == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||
assert (`ICACHE_LINELENINBITS >= 32 | `MEM_ICACHE == 0) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
|
||||
assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size");
|
||||
assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | `MEM_DCACHE==0) else $error("DCACHE_LINELENINBITS must be a power of 2");
|
||||
assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | `MEM_DCACHE==0) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
|
||||
assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS | `MEM_ICACHE==0) else $error("ICACHE_LINELENINBITS must be a power of 2");
|
||||
assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | `MEM_ICACHE==0) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
|
||||
assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES | `MEM_VIRTMEM==0) else $error("ITLB_ENTRIES must be a power of 2");
|
||||
assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `MEM_VIRTMEM==0) else $error("DTLB_ENTRIES must be a power of 2");
|
||||
assert (`RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if RAM_RANGE is less than 56'h07FFFFFF");
|
||||
assert (`ZICSR_SUPPORTED == 1 | (`PMP_ENTRIES == 0 & `MEM_VIRTMEM == 0)) else $error("PMP_ENTRIES and MEM_VIRTMEM must be zero if ZICSR not supported.");
|
||||
assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZISR not supported");
|
||||
assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported");
|
||||
end
|
||||
endmodule
|
||||
|
||||
|
||||
/* verilator lint_on STMTDLY */
|
||||
/* verilator lint_on WIDTH */
|
||||
|
||||
module DCacheFlushFSM
|
||||
(input logic clk,
|
||||
input logic reset,
|
||||
input logic start,
|
||||
output logic done);
|
||||
|
||||
genvar adr;
|
||||
|
||||
logic [`XLEN-1:0] ShadowRAM[`RAM_BASE>>(1+`XLEN/32):(`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32)];
|
||||
|
||||
if(`MEM_DCACHE) begin
|
||||
localparam integer numlines = testbench.dut.hart.lsu.dcache.dcache.NUMLINES;
|
||||
localparam integer numways = testbench.dut.hart.lsu.dcache.dcache.NUMWAYS;
|
||||
localparam integer linebytelen = testbench.dut.hart.lsu.dcache.dcache.LINEBYTELEN;
|
||||
localparam integer numwords = testbench.dut.hart.lsu.dcache.dcache.LINELEN/`XLEN;
|
||||
localparam integer lognumlines = $clog2(numlines);
|
||||
localparam integer loglinebytelen = $clog2(linebytelen);
|
||||
localparam integer lognumways = $clog2(numways);
|
||||
localparam integer tagstart = lognumlines + loglinebytelen;
|
||||
|
||||
|
||||
|
||||
genvar index, way, cacheWord;
|
||||
logic [`XLEN-1:0] CacheData [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
logic CacheValid [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
logic CacheDirty [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
for(index = 0; index < numlines; index++) begin
|
||||
for(way = 0; way < numways; way++) begin
|
||||
for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin
|
||||
copyShadow #(.tagstart(tagstart),
|
||||
.loglinebytelen(loglinebytelen))
|
||||
copyShadow(.clk,
|
||||
.start,
|
||||
.tag(testbench.dut.hart.lsu.dcache.dcache.MemWay[way].CacheTagMem.StoredData[index]),
|
||||
.valid(testbench.dut.hart.lsu.dcache.dcache.MemWay[way].ValidBits[index]),
|
||||
.dirty(testbench.dut.hart.lsu.dcache.dcache.MemWay[way].DirtyBits[index]),
|
||||
.data(testbench.dut.hart.lsu.dcache.dcache.MemWay[way].word[cacheWord].CacheDataMem.StoredData[index]),
|
||||
.index(index),
|
||||
.cacheWord(cacheWord),
|
||||
.CacheData(CacheData[way][index][cacheWord]),
|
||||
.CacheAdr(CacheAdr[way][index][cacheWord]),
|
||||
.CacheTag(CacheTag[way][index][cacheWord]),
|
||||
.CacheValid(CacheValid[way][index][cacheWord]),
|
||||
.CacheDirty(CacheDirty[way][index][cacheWord]));
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
integer i, j, k;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (start) begin #1
|
||||
#1
|
||||
for(i = 0; i < numlines; i++) begin
|
||||
for(j = 0; j < numways; j++) begin
|
||||
for(k = 0; k < numwords; k++) begin
|
||||
if (CacheValid[j][i][k] & CacheDirty[j][i][k]) begin
|
||||
ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = CacheData[j][i][k];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
end
|
||||
flop #(1) doneReg(.clk, .d(start), .q(done));
|
||||
endmodule
|
||||
|
||||
module copyShadow
|
||||
#(parameter tagstart, loglinebytelen)
|
||||
(input logic clk,
|
||||
input logic start,
|
||||
input logic [`PA_BITS-1:tagstart] tag,
|
||||
input logic valid, dirty,
|
||||
input logic [`XLEN-1:0] data,
|
||||
input logic [32-1:0] index,
|
||||
input logic [32-1:0] cacheWord,
|
||||
output logic [`XLEN-1:0] CacheData,
|
||||
output logic [`PA_BITS-1:0] CacheAdr,
|
||||
output logic [`XLEN-1:0] CacheTag,
|
||||
output logic CacheValid,
|
||||
output logic CacheDirty);
|
||||
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if(start) begin
|
||||
CacheTag = tag;
|
||||
CacheValid = valid;
|
||||
CacheDirty = dirty;
|
||||
CacheData = data;
|
||||
CacheAdr = (tag << tagstart) + (index << loglinebytelen) + (cacheWord << $clog2(`XLEN/8));
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
@ -185,9 +185,9 @@ logic [3:0] dummy;
|
||||
else meminit = 64'hFEDCBA9876543210;
|
||||
// *** broken because DTIM also drives RAM
|
||||
if (`TESTSBP) begin
|
||||
for (i=MemStartAddr; i<MemEndAddr; i = i+1) begin
|
||||
dut.uncore.ram.ram.RAM[i] = meminit;
|
||||
end
|
||||
for (i=MemStartAddr; i<MemEndAddr; i = i+1) begin
|
||||
dut.uncore.ram.ram.RAM[i] = meminit;
|
||||
end
|
||||
end
|
||||
// read test vectors into memory
|
||||
pathname = tvpaths[tests[0].atoi()];
|
||||
@ -196,6 +196,7 @@ logic [3:0] dummy;
|
||||
else pathname = tvpaths[1]; */
|
||||
memfilename = {pathname, tests[test], ".elf.memfile"};
|
||||
$readmemh(memfilename, dut.uncore.ram.ram.RAM);
|
||||
//if(`MEM_DTIM == 1) $readmemh(memfilename, dut.hart.lsu.dtim.ram.RAM);
|
||||
ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
|
||||
ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
|
||||
$display("Read memfile %s", memfilename);
|
||||
@ -249,6 +250,7 @@ logic [3:0] dummy;
|
||||
//$display("signature[%h] = %h", i, signature[i]);
|
||||
// *** have to figure out how to exclude shadowram when not using a dcache.
|
||||
if (signature[i] !== dut.uncore.ram.ram.RAM[testadr+i] &
|
||||
//if (signature[i] !== dut.hart.lsu.dtim.ram.RAM[testadr+i] &
|
||||
(signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin
|
||||
if (signature[i+4] !== 'bx | signature[i] !== 32'hFFFFFFFF) begin
|
||||
// report errors unless they are garbage at the end of the sim
|
||||
@ -256,6 +258,7 @@ logic [3:0] dummy;
|
||||
errors = errors+1;
|
||||
$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (TIM) = %h, signature = %h",
|
||||
tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dut.uncore.ram.ram.RAM[testadr+i], signature[i]);
|
||||
// tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dut.hart.lsu.dtim.ram.RAM[testadr+i], signature[i]);
|
||||
$stop;//***debug
|
||||
end
|
||||
end
|
||||
@ -279,6 +282,7 @@ logic [3:0] dummy;
|
||||
//pathname = tvpaths[tests[0]];
|
||||
memfilename = {pathname, tests[test], ".elf.memfile"};
|
||||
$readmemh(memfilename, dut.uncore.ram.ram.RAM);
|
||||
//if(`MEM_DTIM == 1) $readmemh(memfilename, dut.hart.lsu.dtim.ram.RAM);
|
||||
ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
|
||||
ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
|
||||
$display("Read memfile %s", memfilename);
|
||||
|
@ -1,3 +1,5 @@
|
||||
james.stine@okstate.edu 14 Jan 2022
|
||||
|
||||
These are the testvectors (TV) to test the floating-point units using
|
||||
Berkeley TestFloat written originally by John Hauser. TestFloat
|
||||
requires both TestFloat and SoftFloat.
|
||||
@ -12,6 +14,12 @@ createX.sh (e.g., create_vectors32.sh) has been included that create
|
||||
the TV for each rounding mode and operation. These scripts must be
|
||||
run in the build directory of TestFloat.
|
||||
|
||||
A set of scripts is also include that runs everything from the
|
||||
baseline directory. Please change the BUILD and OUTPUT variable to
|
||||
change your baseline program where its compiled and where you want to
|
||||
output the vectors. By default, the vectors are output into the
|
||||
vectors subdirectory.
|
||||
|
||||
After each TV has been created a script (included) is run called
|
||||
undy.sh that puts an underscore between vector to allow SystemVerilog
|
||||
readmemh to read correctly.
|
||||
@ -21,15 +29,15 @@ readmemh to read correctly.
|
||||
To remove all the underscores from all the TV files, one can run the
|
||||
command that will add underscores appropriately to all the files.
|
||||
|
||||
sed -i 's/ /_/g' *.tv
|
||||
cd vectors
|
||||
../undy.sh \*
|
||||
|
||||
Note: due to size, the fxx_fma_xx.tv vectors are not included.
|
||||
However, they can easily be created with the create scripts.
|
||||
|
||||
James Stine
|
||||
10/7/2021
|
||||
|
||||
List of TestVectors (TV) and sizes
|
||||
Although not needed, a case.sh script is included to change the case
|
||||
of the hex output. This is for those that do not like to see
|
||||
hexadecimal capitalized :P.
|
||||
|
||||
46464 185856 836352 f16_add_rd.tv
|
||||
46464 185856 836352 f16_add_rne.tv
|
||||
@ -39,6 +47,10 @@ List of TestVectors (TV) and sizes
|
||||
46464 185856 836352 f16_div_rne.tv
|
||||
46464 185856 836352 f16_div_ru.tv
|
||||
46464 185856 836352 f16_div_rz.tv
|
||||
46464 185856 836352 f16_mul_rd.tv
|
||||
46464 185856 836352 f16_mul_rne.tv
|
||||
46464 185856 836352 f16_mul_ru.tv
|
||||
46464 185856 836352 f16_mul_rz.tv
|
||||
408 1224 5304 f16_sqrt_rd.tv
|
||||
408 1224 5304 f16_sqrt_rne.tv
|
||||
408 1224 5304 f16_sqrt_ru.tv
|
||||
@ -73,10 +85,10 @@ List of TestVectors (TV) and sizes
|
||||
600 1800 17400 f32_i64_rne.tv
|
||||
600 1800 17400 f32_i64_ru.tv
|
||||
600 1800 17400 f32_i64_rz.tv
|
||||
46464 46464 1393920 f32_mul_rd.tv
|
||||
46464 46464 1393920 f32_mul_rne.tv
|
||||
46464 46464 1393920 f32_mul_ru.tv
|
||||
46464 46464 1393920 f32_mul_rz.tv
|
||||
46464 185856 1393920 f32_mul_rd.tv
|
||||
46464 185856 1393920 f32_mul_rne.tv
|
||||
46464 185856 1393920 f32_mul_ru.tv
|
||||
46464 185856 1393920 f32_mul_rz.tv
|
||||
600 1800 12600 f32_sqrt_rd.tv
|
||||
600 1800 12600 f32_sqrt_rne.tv
|
||||
600 1800 12600 f32_sqrt_ru.tv
|
||||
@ -171,4 +183,5 @@ List of TestVectors (TV) and sizes
|
||||
756 2268 27972 ui64_f64_rne.tv
|
||||
756 2268 27972 ui64_f64_ru.tv
|
||||
756 2268 27972 ui64_f64_rz.tv
|
||||
2654496 10007904 91305888 total
|
||||
2840352 11308896 94651296 total
|
||||
|
||||
|
@ -1,22 +1,31 @@
|
||||
#!/bin/sh
|
||||
./testfloat_gen -rnear_even f16_add > f16_add_rne.tv
|
||||
./testfloat_gen -rminMag f16_add > f16_add_rz.tv
|
||||
./testfloat_gen -rmin f16_add > f16_add_ru.tv
|
||||
./testfloat_gen -rmax f16_add > f16_add_rd.tv
|
||||
|
||||
./testfloat_gen -rnear_even f16_sub > f16_sub_rne.tv
|
||||
./testfloat_gen -rminMag f16_sub > f16_sub_rz.tv
|
||||
./testfloat_gen -rmin f16_sub > f16_sub_ru.tv
|
||||
./testfloat_gen -rmax f16_sub > f16_sub_rd.tv
|
||||
BUILD="./TestFloat-3e/build/Linux-x86_64-GCC"
|
||||
OUTPUT="./vectors"
|
||||
|
||||
./testfloat_gen -rnear_even f16_div > f16_div_rne.tv
|
||||
./testfloat_gen -rminMag f16_div > f16_div_rz.tv
|
||||
./testfloat_gen -rmin f16_div > f16_div_ru.tv
|
||||
./testfloat_gen -rmax f16_div > f16_div_rd.tv
|
||||
$BUILD/testfloat_gen -rnear_even f16_add > $OUTPUT/f16_add_rne.tv
|
||||
$BUILD/testfloat_gen -rminMag f16_add > $OUTPUT/f16_add_rz.tv
|
||||
$BUILD/testfloat_gen -rmin f16_add > $OUTPUT/f16_add_ru.tv
|
||||
$BUILD/testfloat_gen -rmax f16_add > $OUTPUT/f16_add_rd.tv
|
||||
|
||||
./testfloat_gen -rnear_even f16_sqrt > f16_sqrt_rne.tv
|
||||
./testfloat_gen -rminMag f16_sqrt > f16_sqrt_rz.tv
|
||||
./testfloat_gen -rmin f16_sqrt > f16_sqrt_ru.tv
|
||||
./testfloat_gen -rmax f16_sqrt > f16_sqrt_rd.tv
|
||||
$BUILD/testfloat_gen -rnear_even f16_sub > $OUTPUT/f16_sub_rne.tv
|
||||
$BUILD/testfloat_gen -rminMag f16_sub > $OUTPUT/f16_sub_rz.tv
|
||||
$BUILD/testfloat_gen -rmin f16_sub > $OUTPUT/f16_sub_ru.tv
|
||||
$BUILD/testfloat_gen -rmax f16_sub > $OUTPUT/f16_sub_rd.tv
|
||||
|
||||
$BUILD/testfloat_gen -rnear_even f16_div > $OUTPUT/f16_div_rne.tv
|
||||
$BUILD/testfloat_gen -rminMag f16_div > $OUTPUT/f16_div_rz.tv
|
||||
$BUILD/testfloat_gen -rmin f16_div > $OUTPUT/f16_div_ru.tv
|
||||
$BUILD/testfloat_gen -rmax f16_div > $OUTPUT/f16_div_rd.tv
|
||||
|
||||
$BUILD/testfloat_gen -rnear_even f16_sqrt > $OUTPUT/f16_sqrt_rne.tv
|
||||
$BUILD/testfloat_gen -rminMag f16_sqrt > $OUTPUT/f16_sqrt_rz.tv
|
||||
$BUILD/testfloat_gen -rmin f16_sqrt > $OUTPUT/f16_sqrt_ru.tv
|
||||
$BUILD/testfloat_gen -rmax f16_sqrt > $OUTPUT/f16_sqrt_rd.tv
|
||||
|
||||
$BUILD/testfloat_gen -rnear_even f16_mul > $OUTPUT/f16_mul_rne.tv
|
||||
$BUILD/testfloat_gen -rminMag f16_mul > $OUTPUT/f16_mul_rz.tv
|
||||
$BUILD/testfloat_gen -rmax f16_mul > $OUTPUT/f16_mul_ru.tv
|
||||
$BUILD/testfloat_gen -rmin f16_mul > $OUTPUT/f16_mul_rd.tv
|
||||
|
||||
|
||||
|
@ -1,20 +1,29 @@
|
||||
#!/bin/sh
|
||||
./testfloat_gen -rnear_even f32_add > f32_add_rne.tv
|
||||
./testfloat_gen -rminMag f32_add > f32_add_rz.tv
|
||||
./testfloat_gen -rmax f32_add > f32_add_ru.tv
|
||||
./testfloat_gen -rmin f32_add > f32_add_rd.tv
|
||||
|
||||
./testfloat_gen -rnear_even f32_sub > f32_sub_rne.tv
|
||||
./testfloat_gen -rminMag f32_sub > f32_sub_rz.tv
|
||||
./testfloat_gen -rmax f32_sub > f32_sub_ru.tv
|
||||
./testfloat_gen -rmin f32_sub > f32_sub_rd.tv
|
||||
BUILD="./TestFloat-3e/build/Linux-x86_64-GCC"
|
||||
OUTPUT="./vectors"
|
||||
|
||||
./testfloat_gen -rnear_even f32_div > f32_div_rne.tv
|
||||
./testfloat_gen -rminMag f32_div > f32_div_rz.tv
|
||||
./testfloat_gen -rmax f32_div > f32_div_ru.tv
|
||||
./testfloat_gen -rmin f32_div > f32_div_rd.tv
|
||||
$BUILD/testfloat_gen -rnear_even f32_add > $OUTPUT/f32_add_rne.tv
|
||||
$BUILD/testfloat_gen -rminMag f32_add > $OUTPUT/f32_add_rz.tv
|
||||
$BUILD/testfloat_gen -rmax f32_add > $OUTPUT/f32_add_ru.tv
|
||||
$BUILD/testfloat_gen -rmin f32_add > $OUTPUT/f32_add_rd.tv
|
||||
|
||||
./testfloat_gen -rnear_even f32_sqrt > f32_sqrt_rne.tv
|
||||
./testfloat_gen -rminMag f32_sqrt > f32_sqrt_rz.tv
|
||||
./testfloat_gen -rmax f32_sqrt > f32_sqrt_ru.tv
|
||||
./testfloat_gen -rmin f32_sqrt > f32_sqrt_rd.tv
|
||||
$BUILD/testfloat_gen -rnear_even f32_sub > $OUTPUT/f32_sub_rne.tv
|
||||
$BUILD/testfloat_gen -rminMag f32_sub > $OUTPUT/f32_sub_rz.tv
|
||||
$BUILD/testfloat_gen -rmax f32_sub > $OUTPUT/f32_sub_ru.tv
|
||||
$BUILD/testfloat_gen -rmin f32_sub > $OUTPUT/f32_sub_rd.tv
|
||||
|
||||
$BUILD/testfloat_gen -rnear_even f32_div > $OUTPUT/f32_div_rne.tv
|
||||
$BUILD/testfloat_gen -rminMag f32_div > $OUTPUT/f32_div_rz.tv
|
||||
$BUILD/testfloat_gen -rmax f32_div > $OUTPUT/f32_div_ru.tv
|
||||
$BUILD/testfloat_gen -rmin f32_div > $OUTPUT/f32_div_rd.tv
|
||||
|
||||
$BUILD/testfloat_gen -rnear_even f32_sqrt > $OUTPUT/f32_sqrt_rne.tv
|
||||
$BUILD/testfloat_gen -rminMag f32_sqrt > $OUTPUT/f32_sqrt_rz.tv
|
||||
$BUILD/testfloat_gen -rmax f32_sqrt > $OUTPUT/f32_sqrt_ru.tv
|
||||
$BUILD/testfloat_gen -rmin f32_sqrt > $OUTPUT/f32_sqrt_rd.tv
|
||||
|
||||
$BUILD/testfloat_gen -rnear_even f32_mul > $OUTPUT/f32_mul_rne.tv
|
||||
$BUILD/testfloat_gen -rminMag f32_mul > $OUTPUT/f32_mul_rz.tv
|
||||
$BUILD/testfloat_gen -rmax f32_mul > $OUTPUT/f32_mul_ru.tv
|
||||
$BUILD/testfloat_gen -rmin f32_mul > $OUTPUT/f32_mul_rd.tv
|
||||
|
@ -1,16 +1,20 @@
|
||||
#!/bin/sh
|
||||
./testfloat_gen -rnear_even f32_to_f64 > f32_f64_rne.tv
|
||||
./testfloat_gen -rminMag f32_to_f64 > f32_f64_rz.tv
|
||||
./testfloat_gen -rmax f32_to_f64 > f32_f64_ru.tv
|
||||
./testfloat_gen -rmin f32_to_f64 > f32_f64_rd.tv
|
||||
|
||||
./testfloat_gen -rnear_even f32_to_i64 > f32_i64_rne.tv
|
||||
./testfloat_gen -rminMag f32_to_i64 > f32_i64_rz.tv
|
||||
./testfloat_gen -rmax f32_to_i64 > f32_i64_ru.tv
|
||||
./testfloat_gen -rmin f32_to_i64 > f32_i64_rd.tv
|
||||
BUILD="./TestFloat-3e/build/Linux-x86_64-GCC"
|
||||
OUTPUT="./vectors"
|
||||
|
||||
./testfloat_gen -rnear_even f32_to_ui64 > f32_ui64_rne.tv
|
||||
./testfloat_gen -rminMag f32_to_ui64 > f32_ui64_rz.tv
|
||||
./testfloat_gen -rmax f32_to_ui64 > f32_ui64_ru.tv
|
||||
./testfloat_gen -rmin f32_to_ui64 > f32_ui64_rd.tv
|
||||
$BUILD/testfloat_gen -rnear_even f32_to_f64 > $OUTPUT/f32_f64_rne.tv
|
||||
$BUILD/testfloat_gen -rminMag f32_to_f64 > $OUTPUT/f32_f64_rz.tv
|
||||
$BUILD/testfloat_gen -rmax f32_to_f64 > $OUTPUT/f32_f64_ru.tv
|
||||
$BUILD/testfloat_gen -rmin f32_to_f64 > $OUTPUT/f32_f64_rd.tv
|
||||
|
||||
$BUILD/testfloat_gen -rnear_even f32_to_i64 > $OUTPUT/f32_i64_rne.tv
|
||||
$BUILD/testfloat_gen -rminMag f32_to_i64 > $OUTPUT/f32_i64_rz.tv
|
||||
$BUILD/testfloat_gen -rmax f32_to_i64 > $OUTPUT/f32_i64_ru.tv
|
||||
$BUILD/testfloat_gen -rmin f32_to_i64 > $OUTPUT/f32_i64_rd.tv
|
||||
|
||||
$BUILD/testfloat_gen -rnear_even f32_to_ui64 > $OUTPUT/f32_ui64_rne.tv
|
||||
$BUILD/testfloat_gen -rminMag f32_to_ui64 > $OUTPUT/f32_ui64_rz.tv
|
||||
$BUILD/testfloat_gen -rmax f32_to_ui64 > $OUTPUT/f32_ui64_ru.tv
|
||||
$BUILD/testfloat_gen -rmin f32_to_ui64 > $OUTPUT/f32_ui64_rd.tv
|
||||
|
||||
|
@ -1,9 +1,13 @@
|
||||
#!/bin/sh
|
||||
./testfloat_gen f32_eq > f32_cmp_eq.tv
|
||||
./testfloat_gen f32_le > f32_cmp_le.tv
|
||||
./testfloat_gen f32_lt > f32_cmp_lt.tv
|
||||
|
||||
./testfloat_gen f32_eq_signaling > f32_cmp_eq_signaling.tv
|
||||
./testfloat_gen f32_le_quiet > f32_cmp_le_quiet.tv
|
||||
./testfloat_gen f32_lt_quiet > f32_cmp_lt_quiet.tv
|
||||
BUILD="./TestFloat-3e/build/Linux-x86_64-GCC"
|
||||
OUTPUT="./vectors"
|
||||
|
||||
$BUILD/testfloat_gen f32_eq > $OUTPUT/f32_cmp_eq.tv
|
||||
$BUILD/testfloat_gen f32_le > $OUTPUT/f32_cmp_le.tv
|
||||
$BUILD/testfloat_gen f32_lt > $OUTPUT/f32_cmp_lt.tv
|
||||
|
||||
$BUILD/testfloat_gen f32_eq_signaling > $OUTPUT/f32_cmp_eq_signaling.tv
|
||||
$BUILD/testfloat_gen f32_le_quiet > $OUTPUT/f32_cmp_le_quiet.tv
|
||||
$BUILD/testfloat_gen f32_lt_quiet > $OUTPUT/f32_cmp_lt_quiet.tv
|
||||
|
||||
|
@ -1,20 +1,30 @@
|
||||
#!/bin/sh
|
||||
./testfloat_gen -rnear_even f64_add > f64_add_rne.tv
|
||||
./testfloat_gen -rminMag f64_add > f64_add_rz.tv
|
||||
./testfloat_gen -rmax f64_add > f64_add_ru.tv
|
||||
./testfloat_gen -rmin f64_add > f64_add_rd.tv
|
||||
|
||||
./testfloat_gen -rnear_even f64_sub > f64_sub_rne.tv
|
||||
./testfloat_gen -rminMag f64_sub > f64_sub_rz.tv
|
||||
./testfloat_gen -rmax f64_sub > f64_sub_ru.tv
|
||||
./testfloat_gen -rmin f64_sub > f64_sub_rd.tv
|
||||
BUILD="./TestFloat-3e/build/Linux-x86_64-GCC"
|
||||
OUTPUT="./vectors"
|
||||
|
||||
./testfloat_gen -rnear_even f64_div > f64_div_rne.tv
|
||||
./testfloat_gen -rminMag f64_div > f64_div_rz.tv
|
||||
./testfloat_gen -rmax f64_div > f64_div_ru.tv
|
||||
./testfloat_gen -rmin f64_div > f64_div_rd.tv
|
||||
$BUILD/testfloat_gen -rnear_even f64_add > $OUTPUT/f64_add_rne.tv
|
||||
$BUILD/testfloat_gen -rminMag f64_add > $OUTPUT/f64_add_rz.tv
|
||||
$BUILD/testfloat_gen -rmax f64_add > $OUTPUT/f64_add_ru.tv
|
||||
$BUILD/testfloat_gen -rmin f64_add > $OUTPUT/f64_add_rd.tv
|
||||
|
||||
$BUILD/testfloat_gen -rnear_even f64_sub > $OUTPUT/f64_sub_rne.tv
|
||||
$BUILD/testfloat_gen -rminMag f64_sub > $OUTPUT/f64_sub_rz.tv
|
||||
$BUILD/testfloat_gen -rmax f64_sub > $OUTPUT/f64_sub_ru.tv
|
||||
$BUILD/testfloat_gen -rmin f64_sub > $OUTPUT/f64_sub_rd.tv
|
||||
|
||||
$BUILD/testfloat_gen -rnear_even f64_div > $OUTPUT/f64_div_rne.tv
|
||||
$BUILD/testfloat_gen -rminMag f64_div > $OUTPUT/f64_div_rz.tv
|
||||
$BUILD/testfloat_gen -rmax f64_div > $OUTPUT/f64_div_ru.tv
|
||||
$BUILD/testfloat_gen -rmin f64_div > $OUTPUT/f64_div_rd.tv
|
||||
|
||||
$BUILD/testfloat_gen -rnear_even f64_sqrt > $OUTPUT/f64_sqrt_rne.tv
|
||||
$BUILD/testfloat_gen -rminMag f64_sqrt > $OUTPUT/f64_sqrt_rz.tv
|
||||
$BUILD/testfloat_gen -rmax f64_sqrt > $OUTPUT/f64_sqrt_ru.tv
|
||||
$BUILD/testfloat_gen -rmin f64_sqrt > $OUTPUT/f64_sqrt_rd.tv
|
||||
|
||||
$BUILD/testfloat_gen -rnear_even f64_mul > $OUTPUT/f64_mul_rne.tv
|
||||
$BUILD/testfloat_gen -rminMag f64_mul > $OUTPUT/f64_mul_rz.tv
|
||||
$BUILD/testfloat_gen -rmax f64_mul > $OUTPUT/f64_mul_ru.tv
|
||||
$BUILD/testfloat_gen -rmin f64_mul > $OUTPUT/f64_mul_rd.tv
|
||||
|
||||
./testfloat_gen -rnear_even f64_sqrt > f64_sqrt_rne.tv
|
||||
./testfloat_gen -rminMag f64_sqrt > f64_sqrt_rz.tv
|
||||
./testfloat_gen -rmax f64_sqrt > f64_sqrt_ru.tv
|
||||
./testfloat_gen -rmin f64_sqrt > f64_sqrt_rd.tv
|
||||
|
@ -1,18 +1,22 @@
|
||||
#!/bin/sh
|
||||
./testfloat_gen -rnear_even f64_to_f32 > f64_f32_rne.tv
|
||||
./testfloat_gen -rminMag f64_to_f32 > f64_f32_rz.tv
|
||||
./testfloat_gen -rmax f64_to_f32 > f64_f32_ru.tv
|
||||
./testfloat_gen -rmin f64_to_f32 > f64_f32_rd.tv
|
||||
|
||||
./testfloat_gen -rnear_even f64_to_i32 > f64_i32_rne.tv
|
||||
./testfloat_gen -rminMag f64_to_i32 > f64_i32_rz.tv
|
||||
./testfloat_gen -rmax f64_to_i32 > f64_i32_ru.tv
|
||||
./testfloat_gen -rmin f64_to_i32 > f64_i32_rd.tv
|
||||
BUILD="./TestFloat-3e/build/Linux-x86_64-GCC"
|
||||
OUTPUT="./vectors"
|
||||
|
||||
./testfloat_gen -rnear_even f64_to_ui32 > f64_ui32_rne.tv
|
||||
./testfloat_gen -rminMag f64_to_ui32 > f64_ui32_rz.tv
|
||||
./testfloat_gen -rmax f64_to_ui32 > f64_ui32_ru.tv
|
||||
./testfloat_gen -rmin f64_to_ui32 > f64_ui32_rd.tv
|
||||
$BUILD/testfloat_gen -rnear_even f64_to_f32 > $OUTPUT/f64_f32_rne.tv
|
||||
$BUILD/testfloat_gen -rminMag f64_to_f32 > $OUTPUT/f64_f32_rz.tv
|
||||
$BUILD/testfloat_gen -rmax f64_to_f32 > $OUTPUT/f64_f32_ru.tv
|
||||
$BUILD/testfloat_gen -rmin f64_to_f32 > $OUTPUT/f64_f32_rd.tv
|
||||
|
||||
$BUILD/testfloat_gen -rnear_even f64_to_i32 > $OUTPUT/f64_i32_rne.tv
|
||||
$BUILD/testfloat_gen -rminMag f64_to_i32 > $OUTPUT/f64_i32_rz.tv
|
||||
$BUILD/testfloat_gen -rmax f64_to_i32 > $OUTPUT/f64_i32_ru.tv
|
||||
$BUILD/testfloat_gen -rmin f64_to_i32 > $OUTPUT/f64_i32_rd.tv
|
||||
|
||||
$BUILD/testfloat_gen -rnear_even f64_to_ui32 > $OUTPUT/f64_ui32_rne.tv
|
||||
$BUILD/testfloat_gen -rminMag f64_to_ui32 > $OUTPUT/f64_ui32_rz.tv
|
||||
$BUILD/testfloat_gen -rmax f64_to_ui32 > $OUTPUT/f64_ui32_ru.tv
|
||||
$BUILD/testfloat_gen -rmin f64_to_ui32 > $OUTPUT/f64_ui32_rd.tv
|
||||
|
||||
|
||||
|
||||
|
@ -1,9 +1,13 @@
|
||||
#!/bin/sh
|
||||
./testfloat_gen f64_eq > f64_cmp_eq.tv
|
||||
./testfloat_gen f64_le > f64_cmp_le.tv
|
||||
./testfloat_gen f64_lt > f64_cmp_lt.tv
|
||||
|
||||
./testfloat_gen f64_eq_signaling > f64_cmp_eq_signaling.tv
|
||||
./testfloat_gen f64_le_quiet > f64_cmp_le_quiet.tv
|
||||
./testfloat_gen f64_lt_quiet > f64_cmp_lt_quiet.tv
|
||||
BUILD="./TestFloat-3e/build/Linux-x86_64-GCC"
|
||||
OUTPUT="./vectors"
|
||||
|
||||
$BUILD/testfloat_gen f64_eq > $OUTPUT/f64_cmp_eq.tv
|
||||
$BUILD/testfloat_gen f64_le > $OUTPUT/f64_cmp_le.tv
|
||||
$BUILD/testfloat_gen f64_lt > $OUTPUT/f64_cmp_lt.tv
|
||||
|
||||
$BUILD/testfloat_gen f64_eq_signaling > $OUTPUT/f64_cmp_eq_signaling.tv
|
||||
$BUILD/testfloat_gen f64_le_quiet > $OUTPUT/f64_cmp_le_quiet.tv
|
||||
$BUILD/testfloat_gen f64_lt_quiet > $OUTPUT/f64_cmp_lt_quiet.tv
|
||||
|
||||
|
@ -1,60 +1,64 @@
|
||||
#!/bin/sh
|
||||
./testfloat_gen -rnear_even -i32_to_f64 > i32_f64_rne.tv
|
||||
./testfloat_gen -rminMag -i32_to_f64 > i32_f64_rz.tv
|
||||
./testfloat_gen -rmax -i32_to_f64 > i32_f64_ru.tv
|
||||
./testfloat_gen -rmin -i32_to_f64 > i32_f64_rd.tv
|
||||
|
||||
./testfloat_gen -rnear_even -i64_to_f64 > i64_f64_rne.tv
|
||||
./testfloat_gen -rminMag -i64_to_f64 > i64_f64_rz.tv
|
||||
./testfloat_gen -rmax -i64_to_f64 > i64_f64_ru.tv
|
||||
./testfloat_gen -rmin -i64_to_f64 > i64_f64_rd.tv
|
||||
BUILD="./TestFloat-3e/build/Linux-x86_64-GCC"
|
||||
OUTPUT="./vectors"
|
||||
|
||||
./testfloat_gen -rnear_even -i32_to_f32 > i32_f32_rne.tv
|
||||
./testfloat_gen -rminMag -i32_to_f32 > i32_f32_rz.tv
|
||||
./testfloat_gen -rmax -i32_to_f32 > i32_f32_ru.tv
|
||||
./testfloat_gen -rmin -i32_to_f32 > i32_f32_rd.tv
|
||||
$BUILD/testfloat_gen -rnear_even -i32_to_f64 > $OUTPUT/i32_f64_rne.tv
|
||||
$BUILD/testfloat_gen -rminMag -i32_to_f64 > $OUTPUT/i32_f64_rz.tv
|
||||
$BUILD/testfloat_gen -rmax -i32_to_f64 > $OUTPUT/i32_f64_ru.tv
|
||||
$BUILD/testfloat_gen -rmin -i32_to_f64 > $OUTPUT/i32_f64_rd.tv
|
||||
|
||||
./testfloat_gen -rnear_even -f32_to_i32 > f32_i32_rne.tv
|
||||
./testfloat_gen -rminMag -f32_to_i32 > f32_i32_rz.tv
|
||||
./testfloat_gen -rmax -f32_to_i32 > f32_i32_ru.tv
|
||||
./testfloat_gen -rmin -f32_to_i32 > f32_i32_rd.tv
|
||||
$BUILD/testfloat_gen -rnear_even -i64_to_f64 > $OUTPUT/i64_f64_rne.tv
|
||||
$BUILD/testfloat_gen -rminMag -i64_to_f64 > $OUTPUT/i64_f64_rz.tv
|
||||
$BUILD/testfloat_gen -rmax -i64_to_f64 > $OUTPUT/i64_f64_ru.tv
|
||||
$BUILD/testfloat_gen -rmin -i64_to_f64 > $OUTPUT/i64_f64_rd.tv
|
||||
|
||||
./testfloat_gen -rnear_even -f32_to_ui32 > f32_ui32_rne.tv
|
||||
./testfloat_gen -rminMag -f32_to_ui32 > f32_ui32_rz.tv
|
||||
./testfloat_gen -rmax -f32_to_ui32 > f32_ui32_ru.tv
|
||||
./testfloat_gen -rmin -f32_to_ui32 > f32_ui32_rd.tv
|
||||
$BUILD/testfloat_gen -rnear_even -i32_to_f32 > $OUTPUT/i32_f32_rne.tv
|
||||
$BUILD/testfloat_gen -rminMag -i32_to_f32 > $OUTPUT/i32_f32_rz.tv
|
||||
$BUILD/testfloat_gen -rmax -i32_to_f32 > $OUTPUT/i32_f32_ru.tv
|
||||
$BUILD/testfloat_gen -rmin -i32_to_f32 > $OUTPUT/i32_f32_rd.tv
|
||||
|
||||
./testfloat_gen -rnear_even -i64_to_f32 > i64_f32_rne.tv
|
||||
./testfloat_gen -rminMag -i64_to_f32 > i64_f32_rz.tv
|
||||
./testfloat_gen -rmax -i64_to_f32 > i64_f32_ru.tv
|
||||
./testfloat_gen -rmin -i64_to_f32 > i64_f32_rd.tv
|
||||
$BUILD/testfloat_gen -rnear_even -f32_to_i32 > $OUTPUT/f32_i32_rne.tv
|
||||
$BUILD/testfloat_gen -rminMag -f32_to_i32 > $OUTPUT/f32_i32_rz.tv
|
||||
$BUILD/testfloat_gen -rmax -f32_to_i32 > $OUTPUT/f32_i32_ru.tv
|
||||
$BUILD/testfloat_gen -rmin -f32_to_i32 > $OUTPUT/f32_i32_rd.tv
|
||||
|
||||
./testfloat_gen -rnear_even -ui32_to_f64 > ui32_f64_rne.tv
|
||||
./testfloat_gen -rminMag -ui32_to_f64 > ui32_f64_rz.tv
|
||||
./testfloat_gen -rmax -ui32_to_f64 > ui32_f64_ru.tv
|
||||
./testfloat_gen -rmin -ui32_to_f64 > ui32_f64_rd.tv
|
||||
$BUILD/testfloat_gen -rnear_even -f32_to_ui32 > $OUTPUT/f32_ui32_rne.tv
|
||||
$BUILD/testfloat_gen -rminMag -f32_to_ui32 > $OUTPUT/f32_ui32_rz.tv
|
||||
$BUILD/testfloat_gen -rmax -f32_to_ui32 > $OUTPUT/f32_ui32_ru.tv
|
||||
$BUILD/testfloat_gen -rmin -f32_to_ui32 > $OUTPUT/f32_ui32_rd.tv
|
||||
|
||||
./testfloat_gen -rnear_even -ui64_to_f64 > ui64_f64_rne.tv
|
||||
./testfloat_gen -rminMag -ui64_to_f64 > ui64_f64_rz.tv
|
||||
./testfloat_gen -rmax -ui64_to_f64 > ui64_f64_ru.tv
|
||||
./testfloat_gen -rmin -ui64_to_f64 > ui64_f64_rd.tv
|
||||
$BUILD/testfloat_gen -rnear_even -i64_to_f32 > $OUTPUT/i64_f32_rne.tv
|
||||
$BUILD/testfloat_gen -rminMag -i64_to_f32 > $OUTPUT/i64_f32_rz.tv
|
||||
$BUILD/testfloat_gen -rmax -i64_to_f32 > $OUTPUT/i64_f32_ru.tv
|
||||
$BUILD/testfloat_gen -rmin -i64_to_f32 > $OUTPUT/i64_f32_rd.tv
|
||||
|
||||
./testfloat_gen -rnear_even -ui32_to_f32 > ui32_f32_rne.tv
|
||||
./testfloat_gen -rminMag -ui32_to_f32 > ui32_f32_rz.tv
|
||||
./testfloat_gen -rmax -ui32_to_f32 > ui32_f32_ru.tv
|
||||
./testfloat_gen -rmin -ui32_to_f32 > ui32_f32_rd.tv
|
||||
$BUILD/testfloat_gen -rnear_even -ui32_to_f64 > $OUTPUT/ui32_f64_rne.tv
|
||||
$BUILD/testfloat_gen -rminMag -ui32_to_f64 > $OUTPUT/ui32_f64_rz.tv
|
||||
$BUILD/testfloat_gen -rmax -ui32_to_f64 > $OUTPUT/ui32_f64_ru.tv
|
||||
$BUILD/testfloat_gen -rmin -ui32_to_f64 > $OUTPUT/ui32_f64_rd.tv
|
||||
|
||||
./testfloat_gen -rnear_even -ui64_to_f32 > ui64_f32_rne.tv
|
||||
./testfloat_gen -rminMag -ui64_to_f32 > ui64_f32_rz.tv
|
||||
./testfloat_gen -rmax -ui64_to_f32 > ui64_f32_ru.tv
|
||||
./testfloat_gen -rmin -ui64_to_f32 > ui64_f32_rd.tv
|
||||
$BUILD/testfloat_gen -rnear_even -ui64_to_f64 > $OUTPUT/ui64_f64_rne.tv
|
||||
$BUILD/testfloat_gen -rminMag -ui64_to_f64 > $OUTPUT/ui64_f64_rz.tv
|
||||
$BUILD/testfloat_gen -rmax -ui64_to_f64 > $OUTPUT/ui64_f64_ru.tv
|
||||
$BUILD/testfloat_gen -rmin -ui64_to_f64 > $OUTPUT/ui64_f64_rd.tv
|
||||
|
||||
./testfloat_gen -rnear_even -f64_to_i64 > f64_i64_rne.tv
|
||||
./testfloat_gen -rminMag -f64_to_i64 > f64_i64_rz.tv
|
||||
./testfloat_gen -rmax -f64_to_i64 > f64_i64_ru.tv
|
||||
./testfloat_gen -rmin -f64_to_i64 > f64_i64_rd.tv
|
||||
$BUILD/testfloat_gen -rnear_even -ui32_to_f32 > $OUTPUT/ui32_f32_rne.tv
|
||||
$BUILD/testfloat_gen -rminMag -ui32_to_f32 > $OUTPUT/ui32_f32_rz.tv
|
||||
$BUILD/testfloat_gen -rmax -ui32_to_f32 > $OUTPUT/ui32_f32_ru.tv
|
||||
$BUILD/testfloat_gen -rmin -ui32_to_f32 > $OUTPUT/ui32_f32_rd.tv
|
||||
|
||||
./testfloat_gen -rnear_even -f64_to_ui64 > f64_ui64_rne.tv
|
||||
./testfloat_gen -rminMag -f64_to_ui64 > f64_ui64_rz.tv
|
||||
./testfloat_gen -rmax -f64_to_ui64 > f64_ui64_ru.tv
|
||||
./testfloat_gen -rmin -f64_to_ui64 > f64_ui64_rd.tv
|
||||
$BUILD/testfloat_gen -rnear_even -ui64_to_f32 > $OUTPUT/ui64_f32_rne.tv
|
||||
$BUILD/testfloat_gen -rminMag -ui64_to_f32 > $OUTPUT/ui64_f32_rz.tv
|
||||
$BUILD/testfloat_gen -rmax -ui64_to_f32 > $OUTPUT/ui64_f32_ru.tv
|
||||
$BUILD/testfloat_gen -rmin -ui64_to_f32 > $OUTPUT/ui64_f32_rd.tv
|
||||
|
||||
$BUILD/testfloat_gen -rnear_even -f64_to_i64 > $OUTPUT/f64_i64_rne.tv
|
||||
$BUILD/testfloat_gen -rminMag -f64_to_i64 > $OUTPUT/f64_i64_rz.tv
|
||||
$BUILD/testfloat_gen -rmax -f64_to_i64 > $OUTPUT/f64_i64_ru.tv
|
||||
$BUILD/testfloat_gen -rmin -f64_to_i64 > $OUTPUT/f64_i64_rd.tv
|
||||
|
||||
$BUILD/testfloat_gen -rnear_even -f64_to_ui64 > $OUTPUT/f64_ui64_rne.tv
|
||||
$BUILD/testfloat_gen -rminMag -f64_to_ui64 > $OUTPUT/f64_ui64_rz.tv
|
||||
$BUILD/testfloat_gen -rmax -f64_to_ui64 > $OUTPUT/f64_ui64_ru.tv
|
||||
$BUILD/testfloat_gen -rmin -f64_to_ui64 > $OUTPUT/f64_ui64_rd.tv
|
||||
|
@ -1,4 +1,5 @@
|
||||
#!/bin/sh
|
||||
|
||||
./create_vectors16.sh
|
||||
./create_vectors32_64.sh
|
||||
./create_vectors32cmp.sh
|
||||
|
Loading…
Reference in New Issue
Block a user