forked from Github_Repos/cvw
Fixed bug in the lsu's write back data. If an AMO was uncached it would not be corrected executed because the write data to the bus would not include the amoalu.
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@ -374,7 +374,10 @@ module lsu
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assign LocalLSUBusAdr = SelUncachedAdr ? LSUPAdrM : DCacheBusAdr ;
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assign LSUBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalLSUBusAdr;
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assign PreLSUBusHWDATA = ReadDataLineSetsM[WordCount];
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assign LSUBusHWDATA = SelUncachedAdr ? WriteDataM : PreLSUBusHWDATA; // *** why is this not FinalWriteDataM? which does not work.
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// exclude the subword write for uncached. We don't read the data first so we cannot
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// select the subword by masking. Subword write also exists inside the uncore to
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// suport subword masking for i/o. I'm not sure if this is necessary.
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assign LSUBusHWDATA = SelUncachedAdr ? FinalAMOWriteDataM : PreLSUBusHWDATA;
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if (`XLEN == 32) assign LSUBusSize = SelUncachedAdr ? LSUFunct3M : 3'b010;
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else assign LSUBusSize = SelUncachedAdr ? LSUFunct3M : 3'b011;
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@ -191,7 +191,7 @@ module uncore (
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// mux could also include external memory
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// AHB Read Multiplexer
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assign HRDATA = ({`XLEN{HSELRamD}} & HREADRam) |
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({`XLEN{HSELEXTD}} & HRDATAEXT) |
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({`XLEN{HSELEXTD}} & HRDATAEXT) |
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({`XLEN{HSELCLINTD}} & HREADCLINT) |
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({`XLEN{HSELPLICD}} & HREADPLIC) |
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({`XLEN{HSELGPIOD}} & HREADGPIO) |
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