Ross Thompson
65632cb7c9
Fixed minor bug in instruction class decoding.
2021-05-24 13:41:14 -05:00
Ross Thompson
72f77656a3
Fixed bug with instruction classification. The class decoder was incorretly labeling jalr acting as both jalr and jr (no link).
2021-05-24 12:37:16 -05:00
James E. Stine
6f38b7633c
Update header for FPadd
2021-05-24 08:28:16 -05:00
Katherine Parry
70968a4ec3
FSD and FLD imperas tests pass
2021-05-23 18:33:14 -04:00
Katherine Parry
06af239e6c
FMV.D.X imperas test passes
2021-05-20 22:17:59 -04:00
bbracker
bf6337f2f7
plic implementation optimizations
2021-05-19 18:10:48 +00:00
Katherine Parry
9464c9022d
floating point infinite loop removed from imperas tests
2021-05-18 10:42:51 -04:00
James E. Stine
e808b06b82
Forgot initialization config for div - apologies
2021-05-17 17:12:27 -05:00
James E. Stine
5506efc115
Add 32/64-bit shifter for update to shifter block
2021-05-17 17:02:13 -05:00
James E. Stine
865b3ee219
Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version
2021-05-17 16:48:51 -05:00
Thomas Fleming
b9e099d53c
Fix comment
2021-05-14 08:06:07 -04:00
Thomas Fleming
ea4e76938e
Remove busy-mmu and fix missing signal
2021-05-14 07:14:20 -04:00
Thomas Fleming
e27bc1cbf7
Clean up MMU code
2021-05-14 07:12:32 -04:00
Thomas Fleming
1ec6ad14f6
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-04 15:22:21 -04:00
bbracker
8a7fc959eb
small synthesis fixes
2021-05-04 15:21:01 -04:00
Thomas Fleming
19ac77d3fa
Fix compiler warning in PMP checker
2021-05-04 15:18:08 -04:00
Ross Thompson
21acc45121
Fixed synthesis bug with icache valid bit.
2021-05-04 13:03:08 -05:00
Ross Thompson
52e4c49bbb
Fixed icache pcmux control for handling miss spill miss.
2021-05-04 11:05:01 -05:00
Thomas Fleming
3a3c88f5b1
Fix bug in PMP checker
...
Now we only enforce PMP regions if at least one is non-null
2021-05-04 03:14:07 -04:00
Thomas Fleming
c9e5af30fa
Disable PMP checker to fix test loops
...
There is a bug in the PMP checker where S or U mode attempts to make a
memory access while no PMP registers are set. We currently treat this as
a failure, when this should instead be allowed.
2021-05-04 01:56:05 -04:00
Thomas Fleming
ad40464557
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-03 23:15:39 -04:00
Domenico Ottolia
c0f054556c
Fix bug with IllegalInstrFaultM not getting correct value
2021-05-03 22:48:03 -04:00
Thomas Fleming
0254ca7bf6
Adjust attributes in PMA checker
2021-05-03 21:58:32 -04:00
David Harris
afd6153044
Rolled back fflush on uart. Use -syncio in Modelsim command line instead.
2021-05-03 20:04:44 -04:00
David Harris
d07a7fd0f8
Flush uart print statements on \n
2021-05-03 19:51:51 -04:00
David Harris
93466a0b2a
Flush uart print statements on \n
2021-05-03 19:41:37 -04:00
David Harris
58ce0fbbcc
Flush uart print statements on \n
2021-05-03 19:37:45 -04:00
David Harris
b66c7b81de
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 19:29:01 -04:00
David Harris
233726e8d8
Flush uart print statements on \n
2021-05-03 19:25:28 -04:00
Ross Thompson
baf29454f1
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 16:57:36 -05:00
Ross Thompson
7f38056879
fixed subtle typo in icache fsm. Was messing up hit spill hit.
...
I believe the mibench qsort benchmark runs after this icache fix.
2021-05-03 16:55:36 -05:00
Domenico Ottolia
5ab86a690b
Fix bug that caused stvec to get the wrong value
2021-05-03 17:54:57 -04:00
Thomas Fleming
ba1afec621
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-03 17:38:13 -04:00
Thomas Fleming
eda5a267ee
Implement PMP checker and revise PMA checker
2021-05-03 17:37:42 -04:00
Thomas Fleming
8dce32fd22
Remove remnants of InstrReadC
2021-05-03 17:36:25 -04:00
Ross Thompson
e145670b15
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 14:53:54 -05:00
Ross Thompson
cdb602c9ce
Removed combinational loops between icache and PMA checker.
2021-05-03 14:51:25 -05:00
Ross Thompson
19a93345b5
Reduced icache to 1 port memory.
2021-05-03 14:47:49 -05:00
Katherine Parry
ff5a809c26
fpu warnings fixed/commented
2021-05-03 19:17:09 +00:00
Thomas Fleming
cfe64e7c24
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/src/ebu/ahblite.sv
2021-05-03 14:02:19 -04:00
Ross Thompson
a54c231489
Eliminated extra register and fixed ports to icache.
...
Still need to support physical tag check and write in icache memory.
Still need to reduce to 1 port SRAM in icache.
I would like to refactor the icache code.
2021-05-03 12:04:54 -05:00
bbracker
c643372e1d
merge conflict resolved -- Ross and I made the same fix
2021-05-03 10:10:42 -04:00
Ross Thompson
c0a4b7cb17
Fixed typo in ifu for bypassing branch predictor.
...
Fixed missing signal name in local history predictor.
2021-05-03 08:56:45 -05:00
David Harris
a37d9b5e8e
Fixed lint error in div
2021-05-03 09:26:12 -04:00
bbracker
9bde239143
ifu lint fixes
2021-05-03 09:25:22 -04:00
bbracker
2368b58cc9
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 09:23:52 -04:00
Katherine Parry
db95151d8d
fpu imperas tests run
2021-05-01 02:18:01 +00:00
bbracker
1fcd43e844
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-30 06:26:35 -04:00
bbracker
182bfdbb0e
rv32 plic test and lint fixes
2021-04-30 06:26:31 -04:00
Domenico Ottolia
d03ca20dc9
Make vectored interrupt trap handling work, and add tests for mtvec with vectored interrupts
2021-04-29 20:42:14 -04:00
