Ross Thompson
4f56e6ff5d
I think I finally fixed a long hidden bug in the replacement policy. The figures in the textbook are correct. There was small bug in the rtl.
2022-12-18 18:30:35 -06:00
Ross Thompson
ebdac1a9d0
Updated tests for fpga and BP.
2022-12-18 16:24:26 -06:00
Ross Thompson
73fd3fe040
Finally fixed the lru bug. It was actually a flush bug all along. At the end of flush writeback FlushAdr is incremented so clearly the dirty bit then clears the wrong set. Must either take an additional cycle to clear dirty and then change the address or clear the dirty bit before the cache bus acknowledgment. Changed it to clear at begining of that line's writeback before actually writting back.
2022-12-17 23:47:49 -06:00
Ross Thompson
cdeccd78e6
At long last found the subtle bug in the LRU.
...
Since the LRU memory is two ports, 1 read and 1 write, a write in cycle 1 to address x should not
forward data to a read from address y in cycle 2.
A read form address x in cycle 2 would still require forwarding.
2022-12-17 10:03:08 -06:00
Ross Thompson
731fbfc851
Oups found a bug with the new flush cache states.
2022-12-16 16:22:40 -06:00
Ross Thompson
b462554896
Cleanup of cache flush fsm enhancement.
2022-12-16 15:36:53 -06:00
Ross Thompson
e425ecac96
Fixed regression-wally to correct remove and mkdir wkdir.
2022-12-16 12:51:21 -06:00
David Harris
4365c99b52
Refactored stalls and flushes, including FDIV flush with FlushE
2022-12-15 10:56:18 -08:00
David Harris
5b040b7935
Regression delete wkdir files to prevent spurious failures
2022-12-15 10:24:58 -08:00
David Harris
f64c0589fe
FPU test list
2022-12-01 10:18:36 -08:00
Ross Thompson
f9ffcf377b
Reverted the IROM/DTIM address range modelsim assignment.
2022-11-30 17:13:33 -06:00
Ross Thompson
bfd238a4fc
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-30 13:30:37 -06:00
Ross Thompson
8692ccbafb
Intermediate commit. Replaced flip flop dirty bit array with sram.
2022-11-30 00:08:31 -06:00
cturek
e28a6901a9
div tests in sim-wally
2022-11-30 02:32:04 +00:00
Ross Thompson
1e2180ef98
Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.
2022-11-29 17:19:31 -06:00
Ross Thompson
179d321683
Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled.
2022-11-29 14:09:48 -06:00
Ross Thompson
ed54959378
Renamed signals in the cache.
2022-11-29 10:52:40 -06:00
Ross Thompson
4e52755c9f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-22 18:07:32 -06:00
cturek
3fbccbf119
Updated testbench/wave for fdivsqrt new start signals
2022-11-22 22:22:26 +00:00
Ross Thompson
84679c0062
Signal name changes for LRU.
2022-11-20 22:31:36 -06:00
Ross Thompson
1a00e7bbee
Changed names of cache signals.
2022-11-13 21:36:12 -06:00
Ross Thompson
5800dfde60
Updated wave file.
2022-11-13 21:34:45 -06:00
Ross Thompson
7311eca5ff
Wavefile update.
2022-11-10 15:48:06 -06:00
Ross Thompson
270a83352f
Found a way to remove the interlock fsm. Dramatically reducing the complexity of virtual memory and page table walks.
2022-10-23 13:46:50 -05:00
Ross Thompson
49a85c7f50
Sort of solved the bit width warning for dtim, irom ranges.
2022-10-19 10:42:19 -05:00
David Harris
6ab6467777
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-14 17:33:36 -07:00
David Harris
1428081742
Removed unused FPU waves
2022-10-14 17:33:32 -07:00
Ross Thompson
47915421c2
Fixed uncached read bug introduced by yesterday's changes.
2022-10-13 11:11:36 -05:00
Ross Thompson
403daecc8e
Modified the do scripts to change the DTIM_RANGE and IROM_RANGE to large values from the defaults.
...
The defaults are used for synthesis.
rv64i and rv32i: DTIM 2KiB, IROM 2KiB
rv32ic: DTIM 4KiB, IROM 16KiB
Regression tests require 8MiB or larger so modelsim overrides.
2022-10-11 10:47:13 -05:00
David Harris
36c0e1d4e9
Removed imperas tests from rv32i/rv64i because the configs lack privileged support expected in the tests. Also cleaned up comment in LSU
2022-10-10 10:22:12 -07:00
David Harris
e4c5754b3a
Made simple RV64 configuration be RV64i. Eliminated rv64ic and rv64fp. Fixed some bugs related to new width
2022-10-10 09:10:55 -07:00
Ross Thompson
b52f593ecb
Reorganized the configs.
2022-10-09 16:46:48 -05:00
Ross Thompson
8d01cf32fc
Updated wavefile.
2022-10-05 14:55:40 -05:00
Kip Macsai-Goren
c4441eb0fa
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-10-04 17:33:54 +00:00
Kip Macsai-Goren
175e824a61
Renamed endianswap to match module name
2022-10-04 17:33:49 +00:00
Ross Thompson
47e936cab3
Renamed signals in EBU.
2022-09-29 18:29:38 -05:00
David Harris
f08d5b23d5
Eliminated store after store stall when no cache; simplified divshiftcalc logic.
2022-09-21 13:02:34 -07:00
Ross Thompson
91fcca9d17
Merged together bram1p1rw with sram1p1rw as sram1p1rw.
...
Fixed a major issue with the real SRAM implemenation.
2022-09-21 12:20:00 -05:00
David Harris
8d1408a9d6
Moved fpu modules into subdirectories
2022-09-20 04:12:05 -07:00
David Harris
362056f53d
Removed unused otfc for Q
2022-09-19 00:43:27 -07:00
Ross Thompson
db56a326c9
renamed multimanager to multicontroller.
2022-09-14 14:03:37 -05:00
Ross Thompson
40e7d2648f
Renamed signals in the LSU.
2022-09-13 11:47:39 -05:00
David Harris
c2f81e309b
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-07 11:11:39 -07:00
David Harris
b0cf73d19c
Running 16-bit square root cases first in testfloat
2022-09-07 11:11:35 -07:00
Ross Thompson
fd4b382ec6
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-07 12:26:50 -05:00
Ross Thompson
54c55b57cb
Named change for ahb tests to be less annoying.
2022-09-07 12:24:41 -05:00
Ross Thompson
6581490f9c
Modified regression tests to add some ahb configurations.
2022-09-07 12:03:58 -05:00
David Harris
29f015810b
Added rv32i config for regression of wally32periph
2022-09-07 09:37:59 -07:00
Ross Thompson
d07c44bcf6
Merge branch 'multimanager' into main
2022-09-07 10:54:27 -05:00
David Harris
8438546d52
Fixed regression for divsqrt radix2
2022-09-07 06:12:23 -07:00
Ross Thompson
9d5a7281b8
Modified ram_ahb to work with different latencies.
2022-09-04 14:46:15 -05:00
David Harris
247ce70348
Fixed lint errors in square root and improved waveforms in testfloat
2022-09-01 15:49:13 -07:00
Ross Thompson
fcd1465de1
Renamed AHBCachebusdp to abhcacheinterface.
2022-08-31 14:12:19 -05:00
Ross Thompson
d06c64094b
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-08-31 11:38:29 -05:00
Ross Thompson
5b8f888e21
Maybe fixed it?
2022-08-30 18:08:34 -05:00
Ross Thompson
ccb3e9e24e
Updates to wave file.
2022-08-30 17:34:36 -05:00
Ross Thompson
96793d15c0
more progress.
2022-08-30 17:32:32 -05:00
Ross Thompson
2d6a6c6e44
Temporary commit.
2022-08-30 15:40:42 -05:00
Ross Thompson
63a824cca1
More progress.
2022-08-30 15:27:19 -05:00
Ross Thompson
a532eb61ba
Progress.
2022-08-30 14:17:00 -05:00
David Harris
5956fbdd62
Fixed checking termination in testfloat testbench
2022-08-30 10:55:21 -07:00
David Harris
81ec1ac858
Separated out radix 2 and radix 4 stages into different modules
2022-08-29 04:26:14 -07:00
David Harris
b4cb9a678a
renamed srt to fdivsqrt
2022-08-29 04:04:05 -07:00
David Harris
35d0a951d2
Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus.
2022-08-27 20:31:09 -07:00
David Harris
3959902c5b
Adding decoding for dtim. Added rv32ic_wally32periph test, which should hang until decoder overrides bus
2022-08-27 05:31:56 -07:00
David Harris
bd6f2444cd
Fixed address decoder hanging buildroot
2022-08-26 22:01:25 -07:00
Ross Thompson
4ad7ccc7f7
Possible fixes for earily messup of rv32ic and rv64ic configs.
2022-08-25 14:42:08 -05:00
Ross Thompson
5cc4f1f1cd
Added generate around uncore.
2022-08-25 10:35:24 -05:00
Ross Thompson
1e1646da90
Added generate around ebu.
2022-08-25 09:24:13 -05:00
Ross Thompson
22e989ac7b
No longer need wally-pipelined-fpga.do.
2022-08-24 18:10:45 -05:00
Ross Thompson
c636387613
Merged testbench-fpga into testbench.
...
Modified SDC to simplify LimitTimers. LimitTimers needs to be 0 for implmementation and 1 for simulation.
2022-08-24 17:52:25 -05:00
Ross Thompson
5301444a61
Changed signal names.
2022-08-17 16:12:04 -05:00
Katherine Parry
8eeca3319c
radix-2 1 copy passes testfloat
2022-08-06 22:54:05 +00:00
David Harris
6ee8036ae7
plic-s debug
2022-08-03 12:33:09 +00:00
Ross Thompson
acd920ae2f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-08-01 22:09:11 -05:00
David Harris
e3b970d3ff
Partitioned fma into separate files
2022-08-01 18:07:38 +00:00
Ross Thompson
01359dbc4b
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-07-31 12:48:51 -05:00
David Harris
449c80b5f7
More work toward riscof tests
2022-07-26 06:19:13 -07:00
David Harris
55ab81e37b
More riscof makefile tuning
2022-07-25 21:15:56 +00:00
David Harris
6b172723bd
Cleaning up Makefiles for riscof to run each set of tests individually and eliminate warnings
2022-07-25 20:50:38 +00:00
Ross Thompson
334008630f
Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested.
2022-07-24 01:20:29 -05:00
Ross Thompson
856ac24686
Removed replay from the config files.
2022-07-24 00:34:11 -05:00
Ross Thompson
e12e6c3acd
Added more i-cache signals to wave file.
2022-07-24 00:24:13 -05:00
Ross Thompson
70032bf8f4
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-07-23 08:41:59 -05:00
Ross Thompson
0f586c9ed3
Possible improvement to cache which removes the cpu_busy states.
2022-07-22 23:20:37 -05:00
Daniel Torres
b726b05d61
fixed wally rv32e tests, updated regression makefile to new testflow
2022-07-22 17:09:46 -07:00
Katherine Parry
ee7932c804
divider sizes reworked to match book
2022-07-22 22:02:04 +00:00
Katherine Parry
270216dd02
radix-4 division integrated into srt - not tested
2022-07-21 19:38:06 +00:00
Ross Thompson
6c8ac7851e
Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction.
2022-07-19 22:42:25 -05:00
Ross Thompson
ffda64587c
Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added.
2022-07-18 23:37:18 -05:00
Katherine Parry
e599f82b29
moved Ss to execute stage
2022-07-18 20:48:56 +00:00
Katherine Parry
921debf930
removed underflow from inexactct calculation
2022-07-18 17:51:18 +00:00
Katherine Parry
e251022269
merged floating-point radix-2 divider with radix-4
2022-07-15 20:16:59 +00:00
Katherine Parry
b069cfbec2
fixed error in divsqrt
2022-07-14 18:16:00 +00:00
Katherine Parry
e05b2a07d2
removed warnings and took a mux out of the critical path
2022-07-12 18:32:17 -07:00
Katherine Parry
2ada8a8bc1
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
2022-07-12 22:37:20 +00:00
Katherine Parry
b728e5054d
variable interations implemented in radix-4 divider
2022-07-11 18:30:21 -07:00
Katherine Parry
cd53ae67d9
moved fpu ieu write data mux to lsu
2022-07-08 23:56:57 +00:00
Katherine Parry
41c16be012
srt divider merged into fpu
2022-07-07 16:01:33 -07:00
slmnemo
c5fd98ba99
sim-buildroot-batch now runs wally-pipelined-batch
...
with option buildroot buildroot-no-trace to boot linux from step 0
2022-07-06 18:06:43 -07:00
