cturek e28a6901a9 div tests in sim-wally		2022-11-30 02:32:04 +00:00
..
slack-notifier
wave-dos	Added generate around uncore.	2022-08-25 10:35:24 -05:00
wkdir
buildrootBugFinder.py
fpga-wave.do	Renamed signals in the cache.	2022-11-29 10:52:40 -06:00
lint-wally	Made simple RV64 configuration be RV64i. Eliminated rv64ic and rv64fp. Fixed some bugs related to new width	2022-10-10 09:10:55 -07:00
linux-wave.do	Renamed signals in the cache.	2022-11-29 10:52:40 -06:00
make-tests.sh
Makefile	More riscof makefile tuning	2022-07-25 21:15:56 +00:00
makefile-memfile	plic-s debug	2022-08-03 12:33:09 +00:00
regression-wally	Removed imperas tests from rv32i/rv64i because the configs lack privileged support expected in the tests. Also cleaned up comment in LSU	2022-10-10 10:22:12 -07:00
sim-buildroot
sim-buildroot-batch	sim-buildroot-batch now runs wally-pipelined-batch	2022-07-06 18:06:43 -07:00
sim-testfloat	Running 16-bit square root cases first in testfloat	2022-09-07 11:11:35 -07:00
sim-testfloat-batch	fixed error in divsqrt	2022-07-14 18:16:00 +00:00
sim-wally	div tests in sim-wally	2022-11-30 02:32:04 +00:00
sim-wally-batch	Renamed endianswap to match module name	2022-10-04 17:33:49 +00:00
testfloat.do	Moved fpu modules into subdirectories	2022-09-20 04:12:05 -07:00
wally-harvard.do
wally-pipelined-batch.do	Modified the do scripts to change the DTIM_RANGE and IROM_RANGE to large values from the defaults.	2022-10-11 10:47:13 -05:00
wally-pipelined.do	Sort of solved the bit width warning for dtim, irom ranges.	2022-10-19 10:42:19 -05:00
wave-all.do	Renamed signals in the cache.	2022-11-29 10:52:40 -06:00
wave-fpu.do	Updated testbench/wave for fdivsqrt new start signals	2022-11-22 22:22:26 +00:00
wave.do	Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.	2022-11-29 17:19:31 -06:00