David Harris b4cb9a678a renamed srt to fdivsqrt		2022-08-29 04:04:05 -07:00
..
slack-notifier
wave-dos	Added generate around uncore.	2022-08-25 10:35:24 -05:00
wkdir
buildrootBugFinder.py
fpga-wave.do	Added generate around uncore.	2022-08-25 10:35:24 -05:00
lint-wally
linux-wave.do	Added generate around uncore.	2022-08-25 10:35:24 -05:00
make-tests.sh
Makefile	More riscof makefile tuning	2022-07-25 21:15:56 +00:00
makefile-memfile	plic-s debug	2022-08-03 12:33:09 +00:00
regression-wally	Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus.	2022-08-27 20:31:09 -07:00
sim-buildroot
sim-buildroot-batch
sim-testfloat	fixed error in divsqrt	2022-07-14 18:16:00 +00:00
sim-testfloat-batch	fixed error in divsqrt	2022-07-14 18:16:00 +00:00
sim-wally	Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus.	2022-08-27 20:31:09 -07:00
sim-wally-batch	Fixed address decoder hanging buildroot	2022-08-26 22:01:25 -07:00
testfloat.do
wally-harvard.do	Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.	2022-01-13 22:21:43 -06:00
wally-pipelined-batch.do	Fixed address decoder hanging buildroot	2022-08-26 22:01:25 -07:00
wally-pipelined.do	Added generate around uncore.	2022-08-25 10:35:24 -05:00
wave-all.do	Added generate around uncore.	2022-08-25 10:35:24 -05:00
wave-fpu.do	renamed srt to fdivsqrt	2022-08-29 04:04:05 -07:00
wave.do	Added generate around uncore.	2022-08-25 10:35:24 -05:00