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578 Commits 14 Branches 1 Tag 31 MiB
3c49fd08f6
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180 Commits

Author SHA1 Message Date
Thomas Fleming
3c49fd08f6 Remove imem from testbenches 2021-04-14 20:20:34 -04:00
bbracker
8f7ddcfdff rv64 interrupt servicing 2021-04-14 10:19:42 -04:00
Noah Boorstin
d66fcbc4ab busybear: use (slightly) less terrible verilog 2021-04-14 00:18:44 -04:00
Noah Boorstin
c75455cc41 busybear testbench updates 
start speculative checking on CSR* satp, *
add some slight delays in some CSR checkings to make them deterministic

I realize this verilog is incredibly un-idiomatic. But I still don't
know of anything better. If you figure it out, please let me know
 2021-04-14 00:00:27 -04:00
bbracker
1ee8feffe5 integrated peripheral testing into existing workflow 2021-04-08 15:31:39 -04:00
bbracker
755e2e5771 merge testbench 2021-04-08 14:28:01 -04:00
Noah Boorstin
14d2ad1e2d try to remove git-lfs stuff 2021-04-08 13:23:11 -04:00
Domenico Ottolia
65abe13f4f Cause an Illegal Instruction Exception when attempting to write readonly CSRs 2021-04-08 05:12:54 -04:00
Thomas Fleming
303c2c4839 Implement support for superpages 2021-04-08 02:44:59 -04:00
Domenico Ottolia
60cf38192b Add privileged tests to testbench 2021-04-07 02:22:08 -04:00
Domenico Ottolia
465d3986b0 Add passing mtval and mepc tests 2021-04-07 02:21:05 -04:00
Noah Boorstin
284d583877 add busybear boot files with git-lfs 2021-04-05 19:38:43 -04:00
Noah Boorstin
0e3f013212 busybear: reenable 'ruthless' CSR checking 2021-04-05 12:53:30 -04:00
bbracker
31c6b2d01f Yee hoo first draft of PLIC plus self-checking tests 2021-04-04 06:40:53 -04:00
Thomas Fleming
dbd5a4320e Merge branch 'mmu' into main 
Conflicts:
	wally-pipelined/src/wally/wallypipelinedhart.sv
 2021-04-03 22:12:52 -04:00
Thomas Fleming
8dfec29f7e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-03 22:09:50 -04:00
Noah Boorstin
f4e5642c62 busybear: temporary stop after 800k instrs 2021-04-03 21:37:57 -04:00
Katherine Parry
d7b1379ab8 Integrated FPU 2021-04-03 20:52:26 +00:00
James E. Stine
0595ae983f Put back imperas testbench until figure out why m_supported is running for rv64ic 2021-04-02 08:19:25 -05:00
James E. Stine
cff08adc3a Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal. 2021-04-02 06:27:37 -05:00
Thomas Fleming
350fe87119 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-01 16:24:06 -04:00
Thomas Fleming
38a0199260 Merge branch 'mmu' of github.com:davidharrishmc/riscv-wally into mmu 2021-04-01 16:23:19 -04:00
Thomas Fleming
fdb20ee1cf Implement sfence.vma and fix tlb writing 2021-04-01 15:55:05 -04:00
Noah Boorstin
75f58c4df5 busybear: temporarially stop checking CSRs 2021-03-31 14:14:32 -04:00
Noah Boorstin
118e846ef7 busybear: clean up questa warnings 2021-03-31 14:04:57 -04:00
Noah Boorstin
43532be770 busybear: clean up questa warnings 2021-03-31 14:02:15 -04:00
Thomas Fleming
eca2427f94 Merge remote-tracking branch 'origin/main' into main 
Bring icache and MMU code together

Conflicts:
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 22:24:47 -04:00
Thomas Fleming
7126ab7864 Complete basic page table walker 2021-03-30 22:19:27 -04:00
Thomas Fleming
0994d03b28 Update virtual memory tests and move to separate folder 2021-03-30 22:18:29 -04:00
Domenico Ottolia
f7cbaeb217 Add one more test to WALLY-CAUSE, and update privileged testgen 2021-03-30 19:44:58 -04:00
Domenico Ottolia
6619a5f44f Add mcause tests to testbench 2021-03-30 17:17:59 -04:00
ushakya22
6b9ae41302 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-30 15:25:07 -04:00
Domenico Ottolia
f134b09a97 Fix bugs with privileged tests 2021-03-25 14:06:05 -04:00
Noah Boorstin
d02c88dab5 busybear: stop NOPing out atomics 
and bump regression to check for 800k instrs, up from 200k
 2021-03-25 13:29:56 -04:00
Teo Ene
a3aa103dc7 Fix typo from last commit 2021-03-24 17:09:58 -05:00
Teo Ene
e43849b82c Updated coremark_bare testbench for IM 2021-03-24 17:04:43 -05:00
Domenico Ottolia
d67e28bf50 re-organize privileged tests to be in rv64p to rv32p folders 2021-03-24 13:51:25 -04:00
Noah Boorstin
849641f31e busybear: add better warning on illegal instruction 
...also it seems that mret is being picked up as an illegal instruction??
 2021-03-22 18:24:35 -04:00
Noah Boorstin
34b8f750ce busybear: temporarially force rf[5] correct after failure to read CSR 2021-03-22 18:12:41 -04:00
Noah Boorstin
77dd0b4504 busybear: allow overwriting read values 2021-03-22 17:28:44 -04:00
Noah Boorstin
7bb31c3287 busybear: finally get the right error 2021-03-22 16:52:22 -04:00
Noah Boorstin
2aa76b27e1 busybear: comment out some debug printing 2021-03-22 14:54:05 -04:00
Noah Boorstin
74bcd9b994 regression: expect 200k instead of 100k busybear instrs 
and a minor busybear bugfix
 2021-03-22 14:47:52 -04:00
Shreya Sanghai
09faa40eb6 fixed minor bugs in testbench 2021-03-18 17:37:10 -04:00
Shreya Sanghai
bbe0957df5 Merge branch 'gshare' into main 
Conflicts:
	wally-pipelined/regression/wave.do
 2021-03-18 17:25:48 -04:00
Teo Ene
57f1ca5259 Switched coremark to RV64IM 2021-03-17 22:39:56 -05:00
Teo Ene
d2fe42d6d0 adapted coremark bare testbench to new dtim RAM HDL 2021-03-17 16:59:02 -05:00
Teo Ene
4fd0ecff69 Temporarily reverted my last few commits 2021-03-17 15:16:01 -05:00
Teo Ene
3e849f99a6 fix to last commit 2021-03-17 15:02:15 -05:00
Teo Ene
dfe6df2e00 Added Ross's addr lab stuff to coremark stuff 2021-03-17 14:50:54 -05:00