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119 Commits

Author SHA1 Message Date
Ross Thompson
60177b92a6 Added additional interlock for itlb miss -> instrPageFault with concurrent memory operation. 2021-07-25 23:14:28 -05:00
Ross Thompson
3e916da36e Removed the hardware page table walker fault state from the icache so that the icache will only unstall CPU for 1 cycle. 
In the dcache we added a register to save the load read data in the event an itlb miss occurs concurrently with
the load in the memory stage.  Under this situation we need to record the load ReadDataM into a temporary register,
SavedReadDataM.  At this time the CPU is stall; however the walker is going to change the address in the dcache
which destroys this data.  When leaving the PTW_READY state via a walker instruction fault or ITLB write we select
this SavedReadDataM so that the CPU can capture it.
 2021-07-22 19:42:19 -05:00
Ross Thompson
551e3491af Moved the ReadDataW register into the datapath. 
The StallW from the hazard unit controls this.
Previously it was in the dcache and controlled by both the HPTW and hazard unit.
This caused an issue when the CPU expected the data to stay constant while
stalled, but the HPTW was causing the data to be modified.
 2021-07-22 14:52:03 -05:00
Ross Thompson
9c90b4bdf7 Fixed bug with the itlb fault not dcache ptw ready state to ready state. 2021-07-22 14:04:56 -05:00
Ross Thompson
313bc5255c Improved address bus names and usages in the walker, dcache, and tlbs. 
Merge branch 'walkerEnhance' into main
 2021-07-21 14:55:09 -05:00
Ross Thompson
365485bd8b Added performance counters for dcache access and dcache miss. 2021-07-19 22:12:20 -05:00
Ross Thompson
4d53b9002f Broken. 
Possible change to walker, dcache, tlb addressing.
Improves the naming of address signals.
But has a problem when the walker finishes the dcache does not get the correct
address on the cycle the DTLB is updated.  This leads to incorrect index
selection in the dcache.
 2021-07-19 10:33:27 -05:00
David Harris
8317be5aed Renamed pagetablewalker to hptw 2021-07-18 04:11:33 -04:00
Ross Thompson
009c5314b4 Fixed LRSC in 64bit version. 32bit version is broken. 2021-07-17 20:58:49 -05:00
David Harris
8d348dacce Started atomics 2021-07-17 21:11:41 -04:00
David Harris
9a86fc899b LSU cleanup 2021-07-17 20:01:03 -04:00
David Harris
d9750c16a5 Pushing HPTWPAdrM flop into LSUArb 2021-07-17 19:39:18 -04:00
David Harris
fc88b3a693 Continued Translation Address Cleanup 2021-07-17 19:09:13 -04:00
David Harris
6536ef8dce Refining address interface between HPTW and LSU 2021-07-17 19:02:18 -04:00
David Harris
2f81e4c70d hptw: Removed NonBusTrapM from LSU 2021-07-17 15:22:24 -04:00
David Harris
a855e0170e hptw: Propagating PageTableEntryF removal through LSU 2021-07-17 15:01:01 -04:00
David Harris
d4eeabe355 hptw: Unified PageTableEntryM and PageTableEntryF outputs of pagetablewalker into PTE 2021-07-17 14:48:44 -04:00
David Harris
87aa527de7 hptw: minor cleanup 2021-07-17 13:40:12 -04:00
David Harris
b65788d165 Replaced separate PageTypeF and PageTypeM with common PageType 2021-07-17 02:31:23 -04:00
Ross Thompson
0b3dc288ec Made furture progress in the mmu tests. 2021-07-16 15:56:06 -05:00
Ross Thompson
6521d2b468 Also changed the shadow ram's dcache copy widths. 
Merge branch 'dcache' into main
 2021-07-16 14:21:09 -05:00
Ross Thompson
46bce70e42 Fixed walker fault interaction with dcache. 2021-07-16 12:22:13 -05:00
Ross Thompson
e0f719d513 Updated the ptw, lsuarb and dcache to hopefully solve the interlock issues. 2021-07-16 11:12:57 -05:00
Ross Thompson
e5d624c1fa Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault. 2021-07-15 11:56:35 -05:00
Ross Thompson
fa26aec588 Merge branch 'main' into dcache 2021-07-15 11:55:20 -05:00
Ross Thompson
8610ef204c Renamed DCacheStall to LSUStall in hart and hazard. 
Added missing logic in lsu.
 2021-07-15 10:16:16 -05:00
Ross Thompson
ba1e1ec231 Finally have the ptw correctly walking through the dcache to update the itlb. 
Still not working fully.
 2021-07-14 22:26:07 -05:00
Ross Thompson
2c946a282f Fixed d cache not honoring StallW for uncache writes and reads. 2021-07-14 17:23:28 -05:00
Ross Thompson
e91501985c Routed CommittedM and PendingInterruptM through the lsu arb. 2021-07-14 16:18:09 -05:00
Ross Thompson
f4295ff097 Separated interruptM into PendingInterruptM and InterruptM. The d cache now takes in both exceptions and PendingInterrupts. 
This solves the committedM issue.
 2021-07-14 15:00:33 -05:00
Ross Thompson
e8bf502bc2 Added CommitedM to data cache output. 2021-07-13 22:43:42 -05:00
Ross Thompson
3e57c899a2 Partially working changes to support uncached memory access. Not sure what CommitedM is. 2021-07-13 17:24:59 -05:00
Ross Thompson
afc1bc9c38 Moved StoreStall into the hazard unit instead of in the d cache. 2021-07-13 13:20:50 -05:00
Ross Thompson
47e16f5629 Fixed back to back store issue. 
Note there is a bug in the lsuarb which needs to arbitrate a few execution stage signals.
 2021-07-13 12:46:20 -05:00
Ross Thompson
b1ceeb40df Loads in modelsim, but the first store double does not function correctly. The write address is wrong so the cache is updated using the wrong address. 
I think this is do to the cycle latency of stores.  We probably need extra muxes to select between MemPAdrM and MemPAdrW depending on if the write is a
full cache block or a word write from the CPU.
 2021-07-09 17:14:54 -05:00
Ross Thompson
ec80cc1820 Lint passes, but I only hope to have loads working. Stores, lr/sc, atomic, are not fully implemented. 
Also faults and the dcache ptw interlock are not implemented.
 2021-07-09 15:16:38 -05:00
Ross Thompson
94c3fde724 Renamed signal in LSU toLSU and fromLSU to toDCache and fromDCache. 2021-07-08 18:03:52 -05:00
David Harris
032c38b7e7 MMU produces page fault when upper bits aren't equal. Renamed input to MMU to be 'Address' and moved translation mux into MMU out of TLB 2021-07-06 15:29:42 -04:00
Ross Thompson
3345ed7ff4 Merged several of the load/store/instruction access faults inside the mmu. 
Still need to figure out what is wrong with the generation of load page fault when dtlb hit.
 2021-07-06 13:43:53 -05:00
Ross Thompson
6e7e318396 Fixed bug in the LSU pagetable walker interlock. 2021-07-06 10:41:36 -05:00
David Harris
694badcc6b Created tlbcontrol module to hide details 2021-07-06 03:25:11 -04:00
David Harris
600e7802dd Renamed Funct3ToLSU/fromLSU -> SizeToLSU/FromLSU and simplified size muxing in lsuArb 2021-07-04 18:56:30 -04:00
David Harris
b0f199b574 Fixed TLB_ENTRIES merge conflict and handling of global PTEs 2021-07-04 18:05:22 -04:00
David Harris
8b707f7703 Added ASID & Global PTE handling to TLB CAM 2021-07-04 17:53:08 -04:00
David Harris
80666f0a71 Added ASID & Global PTE handling to TLB CAM 2021-07-04 17:52:00 -04:00
Ross Thompson
7f62808544 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-04 16:19:39 -05:00
Ross Thompson
5b70eb86b0 relocated lsuarb and pagetable walker inside the lsu. Does not pass busybear or buildroot, but passes rv32ic and rv64ic. 2021-07-04 13:49:38 -05:00
David Harris
7e22ae973e Fixed MPRV and MXR checks in TLB 2021-07-04 13:20:29 -04:00
David Harris
67e191c6f3 Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries 2021-07-04 11:39:59 -04:00
Ross Thompson
043f1e10c5 Added explicit names to lsu, lsuarb and pagetable walker to make the code refactoring process eaiser. 2021-07-03 15:51:25 -05:00
Ross Thompson
7b3716c281 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-02 13:56:49 -05:00
David Harris
c85e0df1ff Optimized PMP checker logic and added support for configurable number of PMP registers 2021-07-02 11:04:13 -04:00
Ross Thompson
2dc349ea6f Fixed the wrong virtual address write into the dtlb. 2021-07-01 16:55:16 -05:00
Ross Thompson
88a18496cf Got some stores working in virtual memory. 2021-07-01 12:49:09 -05:00
Ross Thompson
9ec624702d Major rewrite of ptw to remove combo loop. 2021-06-30 16:25:03 -05:00
Ross Thompson
bc9c944ba0 Don't use this branch walker still broken. 2021-06-28 17:26:11 -05:00
Ross Thompson
d80ebab941 AMO and LR/SC instructions now working correctly. 
Page table walking is not working.
 2021-06-25 15:42:07 -05:00
Ross Thompson
57a7074800 Some progress. Had to change how the page table walker got it's ready. 2021-06-25 15:07:41 -05:00
Ross Thompson
b4a788c341 Working through a combo loop. 2021-06-25 14:49:27 -05:00
Ross Thompson
d6c19e73f4 Regression test runs further. The LSU state machine which fakes the Dcache had a few bugs. MemAccessM needed to be squashed on bus faults. 2021-06-25 11:05:17 -05:00
Kip Macsai-Goren
ac597d78c8 Removed AHB address, etc signals from physical memory checkers, replaced with physical address from cpu or ptw. Passes lint but not simulations. 2021-06-24 19:59:29 -04:00
bbracker
2155a4e485 Revert "fixed forwarding" 
This reverts commit 86e369df52.
 2021-06-24 17:39:37 -04:00
Ross Thompson
6bab454b17 Works until pma checker breaks the simulation by reading HADDR rather than data physical address. 2021-06-24 14:42:59 -05:00
Ross Thompson
aeeaf6d919 Progress. 2021-06-24 13:05:22 -05:00
bbracker
86e369df52 fixed forwarding 2021-06-24 11:20:21 -04:00
Kip Macsai-Goren
c8f80967a6 added a few very simple arbitrations in the lsuArb that pass regression. cleaned up a few unused signals. Added several comments and concerns to lsuarb so I can remember where my thoughts were at the end of the day. 2021-06-23 19:59:06 -04:00
Ross Thompson
286b4b5b26 Partial addition of page table walker arbiter. 2021-06-23 17:03:54 -05:00
Ross Thompson
9b8bcb8e57 Split the ReadDataW bus into two parts in preparation for the data cache. On the AHB side it is now HRDATAW and on the CPU to data cache side it is ReadDataW. lsu.sv now handles the connection between the two. 
Also reorganized the inputs and outputs of lsu and pagetablewalker into connects between CPU, pagetablewalker, and AHB.
Finally add DisableTranslation to TLB as teh pagetablewalker will need to force no translation when active regardless of the state of SATP.
With Kip.
 2021-06-23 16:43:22 -05:00
David Harris
fa51ab9f68 Refactored pmachecker to have adrdecs used in uncore 2021-06-23 01:41:00 -04:00