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341 Commits

Author SHA1 Message Date
David Harris
94daedeed6 Renamed DCACHE to DCACHE_SUPPORTED and ICACHE to ICACHE_SUPPORTED 2023-01-28 18:52:00 -08:00
David Harris
e4e7e827d6 Renamed BUS to BUS_SUPPORTED 2023-01-28 18:35:53 -08:00
David Harris
3906e706fd Removed integer from localparams 2023-01-27 14:40:06 -08:00
Ross Thompson
1439ff02c7 Added comments to lrsc module. 2023-01-23 17:49:47 -06:00
Ross Thompson
e9f435bbda Oups fixed bug from the last commit. 2023-01-23 17:38:30 -06:00
Ross Thompson
af6899472d Another round of cleanup in the LSU. 2023-01-23 17:27:39 -06:00
Ross Thompson
626bcd8608 Removed mark_debug from all source code. 2023-01-20 18:47:36 -06:00
Ross Thompson
74ab386735 More cleanup and formatting. 2023-01-20 12:34:40 -06:00
Ross Thompson
c5169a3e39 Formatting. 2023-01-20 11:51:10 -06:00
Ross Thompson
19e4d0f7cd Cleanup dtim and irom. 2023-01-18 18:44:30 -06:00
Ross Thompson
fb234d506d Formatted subword* and bytemask. 2023-01-18 18:20:22 -06:00
Ross Thompson
469efa61af Formatting. 2023-01-18 18:17:48 -06:00
Ross Thompson
cbf46f417a Formatting. 2023-01-18 18:16:56 -06:00
Ross Thompson
22eee73a45 Formatting. 2023-01-18 18:16:20 -06:00
Ross Thompson
2048edb7a0 Renamed signals in amoalu. 2023-01-18 18:13:18 -06:00
Ross Thompson
40c0e67930 Formatting. 2023-01-18 18:05:11 -06:00
Ross Thompson
2622f5dfb8 Formatting. 2023-01-18 17:56:47 -06:00
Ross Thompson
fc5424fa62 Formatting 2023-01-18 16:58:03 -06:00
Ross Thompson
c34acab1d7 Formating. 2023-01-18 16:47:40 -06:00
Ross Thompson
4b47598138 Moved amoalu to lsu. 2023-01-17 22:45:46 -06:00
Ross Thompson
f146a01344 Cleaned up ahbcacheinterface. 2023-01-17 22:13:56 -06:00
Ross Thompson
d6c80d937c Formatting progress. 2023-01-17 22:10:31 -06:00
Ross Thompson
c75a164f46 Added comments to dtim and ahbcacheinterface. 2023-01-17 21:56:55 -06:00
David Harris
7f68a55b8c Clean up tabs 2023-01-15 18:23:09 -08:00
David Harris
b613722617 trap comments 2023-01-13 19:44:38 -08:00
Ross Thompson
e0867b1840 Completed review of LSU. 2023-01-11 19:06:03 -06:00
Ross Thompson
318ceba34d Improved LSU formating. 2023-01-11 18:52:46 -06:00
Ross Thompson
b60e9730a7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-11 17:15:49 -06:00
David Harris
8c6ddcc15b changed name to CORE-V-WALLY 2023-01-11 15:15:08 -08:00
Ross Thompson
bccef3b39c Updated header for LSU. 2023-01-11 17:15:07 -06:00
David Harris
3ea4dd4898 Changed Wally to CORE-V Wally 2023-01-11 14:03:44 -08:00
David Harris
739c2c8322 Changed MIT license to Solderpad License 2023-01-10 11:35:20 -08:00
David Harris
01525399cc Removed unused signals; added check for atomic in pmachecker 2023-01-07 05:59:56 -08:00
Ross Thompson
a2de53aeeb Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage. 
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
 2022-12-23 15:10:37 -06:00
Ross Thompson
2cc4d66ded Renamed IFU and LSU stalls. 2022-12-22 21:56:33 -06:00
David Harris
e74d47bcb4 Renamed renamed sram to ram 2022-12-20 08:36:45 -08:00
Ross Thompson
7d04675073 Cleanup comments. 2022-12-16 17:08:35 -06:00
Ross Thompson
ffc5bce0b6 Renamed CPUBusy in LSU. 2022-12-11 15:52:51 -06:00
Ross Thompson
c50a2bd8bf Changed CPUBusy to Stall in ebu modules. 2022-12-11 15:51:35 -06:00
Ross Thompson
3ddf509f28 Renamed CPUBusy to Stall in cache. 2022-12-11 15:49:34 -06:00
Ross Thompson
4aadd87679 Moved CPUBusy out of HPTW. 2022-12-11 15:48:00 -06:00
Ross Thompson
1e2180ef98 Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault. 2022-11-29 17:19:31 -06:00
Ross Thompson
f03d5d3ac8 Renamed Flush to FlushStage in the cache. 2022-11-14 14:11:05 -06:00
Ross Thompson
1a00e7bbee Changed names of cache signals. 2022-11-13 21:36:12 -06:00
Ross Thompson
a27b81ef90 Changed IMWriteDataM to IHWriteDataM. 2022-11-13 12:27:48 -06:00
Ross Thompson
90697ef888 Moved all remaining bus logic from the LSU into ahbcacheinterface. 2022-11-11 14:30:32 -06:00
Ross Thompson
64b818c49a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-10 15:46:25 -06:00
Ross Thompson
31d5eabd77 Renamed Word to Beat for ahbcacheinterface. 2022-11-09 17:52:50 -06:00
Ross Thompson
42c0a10d07 Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU). 
FlushW prevents writting the cache, dtim, and bus state.  FlushW still gates HTRANS.
FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to
not stall W if we get a trap.
 2022-11-07 15:50:55 -06:00
David Harris
9b20bf341e Moved lsuvirtmem muxes into hptw 2022-11-07 11:13:34 -08:00