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33312caeb1
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Author SHA1 Message Date
David Harris
33312caeb1 Restored wally-busybear testbench now that graphical sim is working 2021-06-18 12:36:25 -04:00
bbracker
03a45aeef1 restore graphical buildroot sim 2021-06-18 11:58:16 -04:00
Abe
a0a4b09c94 Updated directory coremark_bare's wally-config file to define PMP_ENTRIES 2021-06-18 11:46:25 -04:00
bbracker
5095c73dde Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-18 09:49:37 -04:00
bbracker
4f50dd575d buildroot added to regression because it passes regression 2021-06-18 09:49:30 -04:00
David Harris
580ac1c4df Made MemPAdrM and related signals PA_BITS wide 2021-06-18 09:36:22 -04:00
David Harris
de221ff2d0 Changed physical addresses to PA_BITS in size in MMU and TLB 2021-06-18 09:11:31 -04:00
bbracker
c25905ac70 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-18 08:15:40 -04:00
bbracker
faae30c31c remove unused testbench-busybear.sv 2021-06-18 08:15:19 -04:00
David Harris
df7e373c69 Cleaned up PMAAccessFult logic but it still doesn't accomdate TIM and BootTim depending on AccessRWX 2021-06-18 08:13:15 -04:00
David Harris
35c74348a4 allow all size memory access in CLINT; added underscore to peripheral address symbols 2021-06-18 08:05:50 -04:00
David Harris
336936cc39 Cleaned up name of MTIME register in CSRC 2021-06-18 07:53:49 -04:00
David Harris
de3a0c644b Further cleaning of PMA checker 2021-06-17 22:27:39 -04:00
David Harris
679e507cc6 Added SUPPORTED to each peripheral in each config file 2021-06-17 21:36:32 -04:00
David Harris
4e0546a7a0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-17 18:54:46 -04:00
David Harris
54b6a2dcad added inputs to pmaadrdec 2021-06-17 18:54:39 -04:00
David Harris
da8eb7749f Started simplifying PMA checker 2021-06-17 16:28:06 -04:00
Abe
ef14fff3fc Commit message 2021-06-17 14:49:13 -04:00
bbracker
2bee4eabab added MTIME and MTIMECMP as read-only CSRs; this likely is not the final version 2021-06-17 12:09:10 -04:00
bbracker
b65adbea63 enable TIME CSR for 32 bit mode as well 2021-06-17 11:34:16 -04:00
bbracker
5a661a7392 provide time and timeh CSRs based on CLINT's counter 2021-06-17 08:38:30 -04:00
bbracker
5b96f7fbd7 making linux waveforms more useful 2021-06-17 08:37:37 -04:00
bbracker
9bc5ddf5f2 PMPADDRreg size bugfix; PMPADDR_ARRAY_REGW[15] is now useable 2021-06-17 05:19:36 -04:00
bbracker
b459d0cc80 changed parsedCSRs2] to parsedCSRs 2021-06-17 05:18:14 -04:00
bbracker
c4983f4388 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-17 00:50:14 -04:00
bbracker
6625f74a85 still not sure if QEMU workaround is correct, but here is all linux progress so far 2021-06-17 00:50:02 -04:00
bbracker
7b98e7aa2f mcause test fixes and s-mode interrupt bugfix 2021-06-16 17:37:08 -04:00
bbracker
3b9ecc8275 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-16 16:17:53 -04:00
bracker
f99c91553f chmod +x'd privileged testgen scripts 2021-06-16 10:28:57 -05:00
bbracker
9c883054c7 fixed incorrect expectation fof CLINT spec 2021-06-15 19:24:24 -04:00
David Harris
afdcead5a9 Added page tables to MMU tests 2021-06-15 17:54:13 -04:00
Kip Macsai-Goren
9330c6091a added page table example file, continued work on mmu test 2021-06-15 16:13:37 -04:00
David Harris
5cfb9d489a Started WALLY-MMU 2021-06-15 11:52:16 -04:00
bbracker
16e5e920b8 whoops forgot RV32 2021-06-15 11:33:01 -04:00
bbracker
8298c0959d apply changes to privileged tests 2021-06-15 11:32:10 -04:00
bbracker
cd00e04943 Merge remote-tracking branch 'origin/fixPrivTests' into main 2021-06-15 09:57:46 -04:00
Katherine Parry
4177f4f148 Updated FMA 2021-06-14 13:42:53 -04:00
David Harris
c6ff11c22e disabled Verilator WIDTH warnings in ICCacheCntrl 2021-06-12 19:50:06 -04:00
Ross Thompson
294f01cbd8 fixed the mtime register. 2021-06-11 13:50:13 -05:00
James E. Stine
11c88c15d5 Put repository of fpdivsqrt with RTL-based adder instead of structural implementation 2021-06-11 14:35:22 -04:00
bracker
8794bf1afa attempt no 1: just change out x28s for x31s 2021-06-11 12:39:28 -05:00
David Harris
49b5fa3994 Reverted MIDELEG and MEDELEG to XLEN so busybear passes 2021-06-10 23:47:32 -04:00
David Harris
e41a87be23 Restored counter events 2021-06-10 11:18:58 -04:00
David Harris
d386929c0e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-10 10:47:55 -04:00
David Harris
802238643a Removed two cycles of latency from the DTIM 2021-06-10 10:30:24 -04:00
bbracker
f272cd46d8 peripheral lint fixes 2021-06-10 10:19:10 -04:00
bbracker
d4aeb1c387 merge 2021-06-10 10:03:01 -04:00
bbracker
0321d74562 attempt to fix regression by adding PMP_ENTRIES to configs 2021-06-10 09:59:26 -04:00
bbracker
d9022551c2 buildroot progress -- able to mimic GDB output 2021-06-10 09:58:20 -04:00
bbracker
79e798a641 UART improved and added more reg read side effects 2021-06-10 09:53:48 -04:00