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Configurable RISC-V Processor
993 Commits 14 Branches 1 Tag 31 MiB
Assembly 55.4%
C 27.2%
SystemVerilog 8.2%
Python 2.7%
Stata 2.3%
Other 4.2%
9c883054c7
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bbracker 9c883054c7 fixed incorrect expectation fof CLINT spec
2021-06-15 19:24:24 -04:00
riscv-coremark
sky130
testsBP Added special tests for checking the accuracy of global and gshare branch 2021-06-04 11:01:54 -05:00
wally-pipelined fixed incorrect expectation fof CLINT spec 2021-06-15 19:24:24 -04:00
.gitattributes moved shared constants to a shared directory 2021-06-03 22:41:30 -04:00
.gitignore script for running make and logging output 2021-05-17 22:12:18 -04:00
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README.md

riscv-wally

Configurable RISC-V Processor